clk-s3c2443.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  4. *
  5. * Common Clock Framework support for S3C2443 and following SoCs.
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk/samsung.h>
  9. #include <linux/io.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/reboot.h>
  13. #include <dt-bindings/clock/s3c2443.h>
  14. #include "clk.h"
  15. #include "clk-pll.h"
  16. /* S3C2416 clock controller register offsets */
  17. #define LOCKCON0 0x00
  18. #define LOCKCON1 0x04
  19. #define MPLLCON 0x10
  20. #define EPLLCON 0x18
  21. #define EPLLCON_K 0x1C
  22. #define CLKSRC 0x20
  23. #define CLKDIV0 0x24
  24. #define CLKDIV1 0x28
  25. #define CLKDIV2 0x2C
  26. #define HCLKCON 0x30
  27. #define PCLKCON 0x34
  28. #define SCLKCON 0x38
  29. #define SWRST 0x44
  30. /* the soc types */
  31. enum supported_socs {
  32. S3C2416,
  33. S3C2443,
  34. S3C2450,
  35. };
  36. static void __iomem *reg_base;
  37. /*
  38. * list of controller registers to be saved and restored during a
  39. * suspend/resume cycle.
  40. */
  41. static unsigned long s3c2443_clk_regs[] __initdata = {
  42. LOCKCON0,
  43. LOCKCON1,
  44. MPLLCON,
  45. EPLLCON,
  46. EPLLCON_K,
  47. CLKSRC,
  48. CLKDIV0,
  49. CLKDIV1,
  50. CLKDIV2,
  51. PCLKCON,
  52. HCLKCON,
  53. SCLKCON,
  54. };
  55. PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
  56. PNAME(esysclk_p) = { "epllref", "epll" };
  57. PNAME(mpllref_p) = { "xti", "mdivclk" };
  58. PNAME(msysclk_p) = { "mpllref", "mpll" };
  59. PNAME(armclk_p) = { "armdiv" , "hclk" };
  60. PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
  61. static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
  62. MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
  63. MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
  64. MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
  65. MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
  66. MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
  67. MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
  68. };
  69. static struct clk_div_table hclk_d[] = {
  70. { .val = 0, .div = 1 },
  71. { .val = 1, .div = 2 },
  72. { .val = 3, .div = 4 },
  73. { /* sentinel */ },
  74. };
  75. static struct clk_div_table mdivclk_d[] = {
  76. { .val = 0, .div = 1 },
  77. { .val = 1, .div = 3 },
  78. { .val = 2, .div = 5 },
  79. { .val = 3, .div = 7 },
  80. { .val = 4, .div = 9 },
  81. { .val = 5, .div = 11 },
  82. { .val = 6, .div = 13 },
  83. { .val = 7, .div = 15 },
  84. { /* sentinel */ },
  85. };
  86. static struct samsung_div_clock s3c2443_common_dividers[] __initdata = {
  87. DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d),
  88. DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2),
  89. DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
  90. DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
  91. DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2),
  92. DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8),
  93. DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4),
  94. DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4),
  95. DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2),
  96. DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2),
  97. };
  98. static struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
  99. GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
  100. GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
  101. GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
  102. GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
  103. GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
  104. GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
  105. GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
  106. GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
  107. GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
  108. GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
  109. GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
  110. GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
  111. GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
  112. GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
  113. GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
  114. GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
  115. GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
  116. GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
  117. GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
  118. GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
  119. GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
  120. GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
  121. GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
  122. GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
  123. GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
  124. GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
  125. GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
  126. GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
  127. GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
  128. GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
  129. GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
  130. };
  131. static struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
  132. ALIAS(MSYSCLK, NULL, "msysclk"),
  133. ALIAS(ARMCLK, NULL, "armclk"),
  134. ALIAS(MPLL, NULL, "mpll"),
  135. ALIAS(EPLL, NULL, "epll"),
  136. ALIAS(HCLK, NULL, "hclk"),
  137. ALIAS(HCLK_SSMC, NULL, "nand"),
  138. ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
  139. ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
  140. ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
  141. ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"),
  142. ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
  143. ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
  144. ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
  145. ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"),
  146. ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
  147. ALIAS(PCLK_PWM, NULL, "timers"),
  148. ALIAS(PCLK_RTC, NULL, "rtc"),
  149. ALIAS(PCLK_WDT, NULL, "watchdog"),
  150. ALIAS(PCLK_ADC, NULL, "adc"),
  151. ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"),
  152. ALIAS(HCLK_USBD, NULL, "usb-device"),
  153. ALIAS(HCLK_USBH, NULL, "usb-host"),
  154. ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
  155. ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"),
  156. ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"),
  157. ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
  158. ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
  159. ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"),
  160. ALIAS(SCLK_I2S0, NULL, "i2s-if"),
  161. ALIAS(HCLK_LCD, NULL, "lcd"),
  162. ALIAS(SCLK_FIMD, NULL, "sclk_fimd"),
  163. };
  164. /* S3C2416 specific clocks */
  165. static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
  166. PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
  167. PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
  168. };
  169. PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
  170. PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
  171. PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
  172. static struct clk_div_table armdiv_s3c2416_d[] = {
  173. { .val = 0, .div = 1 },
  174. { .val = 1, .div = 2 },
  175. { .val = 2, .div = 3 },
  176. { .val = 3, .div = 4 },
  177. { .val = 5, .div = 6 },
  178. { .val = 7, .div = 8 },
  179. { /* sentinel */ },
  180. };
  181. static struct samsung_div_clock s3c2416_dividers[] __initdata = {
  182. DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d),
  183. DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4),
  184. DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2),
  185. };
  186. static struct samsung_mux_clock s3c2416_muxes[] __initdata = {
  187. MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
  188. MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
  189. MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
  190. };
  191. static struct samsung_gate_clock s3c2416_gates[] __initdata = {
  192. GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
  193. GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
  194. GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
  195. GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
  196. GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
  197. GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
  198. GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
  199. };
  200. static struct samsung_clock_alias s3c2416_aliases[] __initdata = {
  201. ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
  202. ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
  203. ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"),
  204. ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
  205. ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
  206. ALIAS(ARMDIV, NULL, "armdiv"),
  207. };
  208. /* S3C2443 specific clocks */
  209. static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
  210. PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
  211. PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
  212. };
  213. static struct clk_div_table armdiv_s3c2443_d[] = {
  214. { .val = 0, .div = 1 },
  215. { .val = 8, .div = 2 },
  216. { .val = 2, .div = 3 },
  217. { .val = 9, .div = 4 },
  218. { .val = 10, .div = 6 },
  219. { .val = 11, .div = 8 },
  220. { .val = 13, .div = 12 },
  221. { .val = 15, .div = 16 },
  222. { /* sentinel */ },
  223. };
  224. static struct samsung_div_clock s3c2443_dividers[] __initdata = {
  225. DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d),
  226. DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
  227. };
  228. static struct samsung_gate_clock s3c2443_gates[] __initdata = {
  229. GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
  230. GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
  231. GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
  232. GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
  233. GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
  234. GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
  235. };
  236. static struct samsung_clock_alias s3c2443_aliases[] __initdata = {
  237. ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
  238. ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
  239. ALIAS(SCLK_CAM, NULL, "camif-upll"),
  240. ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"),
  241. ALIAS(PCLK_SDI, NULL, "sdi"),
  242. ALIAS(HCLK_CFC, NULL, "cfc"),
  243. ALIAS(ARMDIV, NULL, "armdiv"),
  244. };
  245. /* S3C2450 specific clocks */
  246. PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
  247. PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" };
  248. PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
  249. static struct samsung_div_clock s3c2450_dividers[] __initdata = {
  250. DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
  251. DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2),
  252. DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4),
  253. DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4),
  254. };
  255. static struct samsung_mux_clock s3c2450_muxes[] __initdata = {
  256. MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
  257. MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1),
  258. MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2),
  259. };
  260. static struct samsung_gate_clock s3c2450_gates[] __initdata = {
  261. GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
  262. GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
  263. GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
  264. GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
  265. GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
  266. GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
  267. GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
  268. GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),
  269. };
  270. static struct samsung_clock_alias s3c2450_aliases[] __initdata = {
  271. ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"),
  272. ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"),
  273. ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"),
  274. ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"),
  275. };
  276. static int s3c2443_restart(struct notifier_block *this,
  277. unsigned long mode, void *cmd)
  278. {
  279. __raw_writel(0x533c2443, reg_base + SWRST);
  280. return NOTIFY_DONE;
  281. }
  282. static struct notifier_block s3c2443_restart_handler = {
  283. .notifier_call = s3c2443_restart,
  284. .priority = 129,
  285. };
  286. /*
  287. * fixed rate clocks generated outside the soc
  288. * Only necessary until the devicetree-move is complete
  289. */
  290. static struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
  291. FRATE(0, "xti", NULL, 0, 0),
  292. FRATE(0, "ext", NULL, 0, 0),
  293. FRATE(0, "ext_i2s", NULL, 0, 0),
  294. FRATE(0, "ext_uart", NULL, 0, 0),
  295. };
  296. static void __init s3c2443_common_clk_register_fixed_ext(
  297. struct samsung_clk_provider *ctx, unsigned long xti_f)
  298. {
  299. s3c2443_common_frate_clks[0].fixed_rate = xti_f;
  300. samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
  301. ARRAY_SIZE(s3c2443_common_frate_clks));
  302. }
  303. void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
  304. int current_soc,
  305. void __iomem *base)
  306. {
  307. struct samsung_clk_provider *ctx;
  308. int ret;
  309. reg_base = base;
  310. if (np) {
  311. reg_base = of_iomap(np, 0);
  312. if (!reg_base)
  313. panic("%s: failed to map registers\n", __func__);
  314. }
  315. ctx = samsung_clk_init(np, reg_base, NR_CLKS);
  316. /* Register external clocks only in non-dt cases */
  317. if (!np)
  318. s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
  319. /* Register PLLs. */
  320. if (current_soc == S3C2416 || current_soc == S3C2450)
  321. samsung_clk_register_pll(ctx, s3c2416_pll_clks,
  322. ARRAY_SIZE(s3c2416_pll_clks), reg_base);
  323. else
  324. samsung_clk_register_pll(ctx, s3c2443_pll_clks,
  325. ARRAY_SIZE(s3c2443_pll_clks), reg_base);
  326. /* Register common internal clocks. */
  327. samsung_clk_register_mux(ctx, s3c2443_common_muxes,
  328. ARRAY_SIZE(s3c2443_common_muxes));
  329. samsung_clk_register_div(ctx, s3c2443_common_dividers,
  330. ARRAY_SIZE(s3c2443_common_dividers));
  331. samsung_clk_register_gate(ctx, s3c2443_common_gates,
  332. ARRAY_SIZE(s3c2443_common_gates));
  333. samsung_clk_register_alias(ctx, s3c2443_common_aliases,
  334. ARRAY_SIZE(s3c2443_common_aliases));
  335. /* Register SoC-specific clocks. */
  336. switch (current_soc) {
  337. case S3C2450:
  338. samsung_clk_register_div(ctx, s3c2450_dividers,
  339. ARRAY_SIZE(s3c2450_dividers));
  340. samsung_clk_register_mux(ctx, s3c2450_muxes,
  341. ARRAY_SIZE(s3c2450_muxes));
  342. samsung_clk_register_gate(ctx, s3c2450_gates,
  343. ARRAY_SIZE(s3c2450_gates));
  344. samsung_clk_register_alias(ctx, s3c2450_aliases,
  345. ARRAY_SIZE(s3c2450_aliases));
  346. fallthrough; /* as s3c2450 extends the s3c2416 clocks */
  347. case S3C2416:
  348. samsung_clk_register_div(ctx, s3c2416_dividers,
  349. ARRAY_SIZE(s3c2416_dividers));
  350. samsung_clk_register_mux(ctx, s3c2416_muxes,
  351. ARRAY_SIZE(s3c2416_muxes));
  352. samsung_clk_register_gate(ctx, s3c2416_gates,
  353. ARRAY_SIZE(s3c2416_gates));
  354. samsung_clk_register_alias(ctx, s3c2416_aliases,
  355. ARRAY_SIZE(s3c2416_aliases));
  356. break;
  357. case S3C2443:
  358. samsung_clk_register_div(ctx, s3c2443_dividers,
  359. ARRAY_SIZE(s3c2443_dividers));
  360. samsung_clk_register_gate(ctx, s3c2443_gates,
  361. ARRAY_SIZE(s3c2443_gates));
  362. samsung_clk_register_alias(ctx, s3c2443_aliases,
  363. ARRAY_SIZE(s3c2443_aliases));
  364. break;
  365. }
  366. samsung_clk_sleep_init(reg_base, s3c2443_clk_regs,
  367. ARRAY_SIZE(s3c2443_clk_regs));
  368. samsung_clk_of_add_provider(np, ctx);
  369. ret = register_restart_handler(&s3c2443_restart_handler);
  370. if (ret)
  371. pr_warn("cannot register restart handler, %d\n", ret);
  372. }
  373. static void __init s3c2416_clk_init(struct device_node *np)
  374. {
  375. s3c2443_common_clk_init(np, 0, S3C2416, NULL);
  376. }
  377. CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init);
  378. static void __init s3c2443_clk_init(struct device_node *np)
  379. {
  380. s3c2443_common_clk_init(np, 0, S3C2443, NULL);
  381. }
  382. CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init);
  383. static void __init s3c2450_clk_init(struct device_node *np)
  384. {
  385. s3c2443_common_clk_init(np, 0, S3C2450, NULL);
  386. }
  387. CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init);