clk-s3c2410.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  4. *
  5. * Common Clock Framework support for S3C2410 and following SoCs.
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/clk/samsung.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <dt-bindings/clock/s3c2410.h>
  12. #include "clk.h"
  13. #include "clk-pll.h"
  14. #define LOCKTIME 0x00
  15. #define MPLLCON 0x04
  16. #define UPLLCON 0x08
  17. #define CLKCON 0x0c
  18. #define CLKSLOW 0x10
  19. #define CLKDIVN 0x14
  20. #define CAMDIVN 0x18
  21. /* the soc types */
  22. enum supported_socs {
  23. S3C2410,
  24. S3C2440,
  25. S3C2442,
  26. };
  27. /* list of PLLs to be registered */
  28. enum s3c2410_plls {
  29. mpll, upll,
  30. };
  31. static void __iomem *reg_base;
  32. /*
  33. * list of controller registers to be saved and restored during a
  34. * suspend/resume cycle.
  35. */
  36. static unsigned long s3c2410_clk_regs[] __initdata = {
  37. LOCKTIME,
  38. MPLLCON,
  39. UPLLCON,
  40. CLKCON,
  41. CLKSLOW,
  42. CLKDIVN,
  43. CAMDIVN,
  44. };
  45. PNAME(fclk_p) = { "mpll", "div_slow" };
  46. static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
  47. MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
  48. };
  49. static struct clk_div_table divslow_d[] = {
  50. { .val = 0, .div = 1 },
  51. { .val = 1, .div = 2 },
  52. { .val = 2, .div = 4 },
  53. { .val = 3, .div = 6 },
  54. { .val = 4, .div = 8 },
  55. { .val = 5, .div = 10 },
  56. { .val = 6, .div = 12 },
  57. { .val = 7, .div = 14 },
  58. { /* sentinel */ },
  59. };
  60. static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
  61. DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
  62. DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
  63. };
  64. static struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
  65. GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
  66. GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
  67. GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
  68. GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
  69. GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
  70. GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
  71. GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
  72. GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
  73. GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
  74. GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
  75. GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
  76. GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
  77. GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
  78. GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
  79. GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
  80. };
  81. /* should be added _after_ the soc-specific clocks are created */
  82. static struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
  83. ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
  84. ALIAS(PCLK_ADC, NULL, "adc"),
  85. ALIAS(PCLK_RTC, NULL, "rtc"),
  86. ALIAS(PCLK_PWM, NULL, "timers"),
  87. ALIAS(HCLK_LCD, NULL, "lcd"),
  88. ALIAS(HCLK_USBD, NULL, "usb-device"),
  89. ALIAS(HCLK_USBH, NULL, "usb-host"),
  90. ALIAS(UCLK, NULL, "usb-bus-host"),
  91. ALIAS(UCLK, NULL, "usb-bus-gadget"),
  92. ALIAS(ARMCLK, NULL, "armclk"),
  93. ALIAS(UCLK, NULL, "uclk"),
  94. ALIAS(HCLK, NULL, "hclk"),
  95. ALIAS(MPLL, NULL, "mpll"),
  96. ALIAS(FCLK, NULL, "fclk"),
  97. ALIAS(PCLK, NULL, "watchdog"),
  98. ALIAS(PCLK_SDI, NULL, "sdi"),
  99. ALIAS(HCLK_NAND, NULL, "nand"),
  100. ALIAS(PCLK_I2S, NULL, "iis"),
  101. ALIAS(PCLK_I2C, NULL, "i2c"),
  102. };
  103. /* S3C2410 specific clocks */
  104. static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
  105. /* sorted in descending order */
  106. /* 2410A extras */
  107. PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
  108. PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
  109. PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
  110. PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
  111. PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
  112. /* 2410 common */
  113. PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
  114. PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
  115. PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
  116. PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
  117. PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
  118. PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
  119. PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
  120. PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
  121. PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
  122. PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
  123. PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
  124. PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
  125. PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
  126. PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
  127. PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
  128. PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
  129. PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
  130. PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
  131. PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
  132. PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
  133. PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
  134. PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
  135. { /* sentinel */ },
  136. };
  137. static struct samsung_pll_clock s3c2410_plls[] __initdata = {
  138. [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
  139. LOCKTIME, MPLLCON, NULL),
  140. [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
  141. LOCKTIME, UPLLCON, NULL),
  142. };
  143. static struct samsung_div_clock s3c2410_dividers[] __initdata = {
  144. DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
  145. };
  146. static struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
  147. /*
  148. * armclk is directly supplied by the fclk, without
  149. * switching possibility like on the s3c244x below.
  150. */
  151. FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
  152. /* uclk is fed from the unmodified upll */
  153. FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
  154. };
  155. static struct samsung_clock_alias s3c2410_aliases[] __initdata = {
  156. ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
  157. ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
  158. ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
  159. ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
  160. ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
  161. ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
  162. ALIAS(UCLK, NULL, "clk_uart_baud1"),
  163. };
  164. /* S3C244x specific clocks */
  165. static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
  166. /* sorted in descending order */
  167. PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
  168. PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
  169. PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
  170. PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
  171. PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
  172. PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
  173. PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
  174. PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
  175. PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
  176. PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
  177. PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
  178. PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
  179. PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
  180. PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
  181. PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
  182. PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
  183. PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
  184. PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
  185. PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
  186. PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
  187. PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
  188. PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
  189. PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
  190. PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
  191. PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
  192. PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
  193. PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
  194. { /* sentinel */ },
  195. };
  196. static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
  197. [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
  198. LOCKTIME, MPLLCON, NULL),
  199. [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
  200. LOCKTIME, UPLLCON, NULL),
  201. };
  202. PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
  203. PNAME(armclk_p) = { "fclk", "hclk" };
  204. static struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
  205. MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
  206. MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
  207. };
  208. static struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
  209. FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
  210. FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
  211. };
  212. static struct clk_div_table div_hclk_4_d[] = {
  213. { .val = 0, .div = 4 },
  214. { .val = 1, .div = 8 },
  215. { /* sentinel */ },
  216. };
  217. static struct clk_div_table div_hclk_3_d[] = {
  218. { .val = 0, .div = 3 },
  219. { .val = 1, .div = 6 },
  220. { /* sentinel */ },
  221. };
  222. static struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
  223. DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
  224. DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
  225. DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
  226. DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
  227. DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
  228. };
  229. static struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
  230. GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
  231. };
  232. static struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
  233. ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
  234. ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
  235. ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
  236. ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
  237. ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
  238. ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
  239. ALIAS(HCLK_CAM, NULL, "camif"),
  240. ALIAS(CAMIF, NULL, "camif-upll"),
  241. };
  242. /* S3C2440 specific clocks */
  243. PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
  244. static struct samsung_mux_clock s3c2440_muxes[] __initdata = {
  245. MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
  246. };
  247. static struct samsung_gate_clock s3c2440_gates[] __initdata = {
  248. GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
  249. };
  250. /* S3C2442 specific clocks */
  251. static struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
  252. FFACTOR(0, "upll_3", "upll", 1, 3, 0),
  253. };
  254. PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
  255. static struct samsung_mux_clock s3c2442_muxes[] __initdata = {
  256. MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
  257. };
  258. /*
  259. * fixed rate clocks generated outside the soc
  260. * Only necessary until the devicetree-move is complete
  261. */
  262. #define XTI 1
  263. static struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
  264. FRATE(XTI, "xti", NULL, 0, 0),
  265. };
  266. static void __init s3c2410_common_clk_register_fixed_ext(
  267. struct samsung_clk_provider *ctx,
  268. unsigned long xti_f)
  269. {
  270. struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
  271. s3c2410_common_frate_clks[0].fixed_rate = xti_f;
  272. samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
  273. ARRAY_SIZE(s3c2410_common_frate_clks));
  274. samsung_clk_register_alias(ctx, &xti_alias, 1);
  275. }
  276. void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
  277. int current_soc,
  278. void __iomem *base)
  279. {
  280. struct samsung_clk_provider *ctx;
  281. reg_base = base;
  282. if (np) {
  283. reg_base = of_iomap(np, 0);
  284. if (!reg_base)
  285. panic("%s: failed to map registers\n", __func__);
  286. }
  287. ctx = samsung_clk_init(np, reg_base, NR_CLKS);
  288. /* Register external clocks only in non-dt cases */
  289. if (!np)
  290. s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
  291. if (current_soc == S3C2410) {
  292. if (_get_rate("xti") == 12 * MHZ) {
  293. s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
  294. s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
  295. }
  296. /* Register PLLs. */
  297. samsung_clk_register_pll(ctx, s3c2410_plls,
  298. ARRAY_SIZE(s3c2410_plls), reg_base);
  299. } else { /* S3C2440, S3C2442 */
  300. if (_get_rate("xti") == 12 * MHZ) {
  301. /*
  302. * plls follow different calculation schemes, with the
  303. * upll following the same scheme as the s3c2410 plls
  304. */
  305. s3c244x_common_plls[mpll].rate_table =
  306. pll_s3c244x_12mhz_tbl;
  307. s3c244x_common_plls[upll].rate_table =
  308. pll_s3c2410_12mhz_tbl;
  309. }
  310. /* Register PLLs. */
  311. samsung_clk_register_pll(ctx, s3c244x_common_plls,
  312. ARRAY_SIZE(s3c244x_common_plls), reg_base);
  313. }
  314. /* Register common internal clocks. */
  315. samsung_clk_register_mux(ctx, s3c2410_common_muxes,
  316. ARRAY_SIZE(s3c2410_common_muxes));
  317. samsung_clk_register_div(ctx, s3c2410_common_dividers,
  318. ARRAY_SIZE(s3c2410_common_dividers));
  319. samsung_clk_register_gate(ctx, s3c2410_common_gates,
  320. ARRAY_SIZE(s3c2410_common_gates));
  321. if (current_soc == S3C2440 || current_soc == S3C2442) {
  322. samsung_clk_register_div(ctx, s3c244x_common_dividers,
  323. ARRAY_SIZE(s3c244x_common_dividers));
  324. samsung_clk_register_gate(ctx, s3c244x_common_gates,
  325. ARRAY_SIZE(s3c244x_common_gates));
  326. samsung_clk_register_mux(ctx, s3c244x_common_muxes,
  327. ARRAY_SIZE(s3c244x_common_muxes));
  328. samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
  329. ARRAY_SIZE(s3c244x_common_ffactor));
  330. }
  331. /* Register SoC-specific clocks. */
  332. switch (current_soc) {
  333. case S3C2410:
  334. samsung_clk_register_div(ctx, s3c2410_dividers,
  335. ARRAY_SIZE(s3c2410_dividers));
  336. samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
  337. ARRAY_SIZE(s3c2410_ffactor));
  338. samsung_clk_register_alias(ctx, s3c2410_aliases,
  339. ARRAY_SIZE(s3c2410_aliases));
  340. break;
  341. case S3C2440:
  342. samsung_clk_register_mux(ctx, s3c2440_muxes,
  343. ARRAY_SIZE(s3c2440_muxes));
  344. samsung_clk_register_gate(ctx, s3c2440_gates,
  345. ARRAY_SIZE(s3c2440_gates));
  346. break;
  347. case S3C2442:
  348. samsung_clk_register_mux(ctx, s3c2442_muxes,
  349. ARRAY_SIZE(s3c2442_muxes));
  350. samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
  351. ARRAY_SIZE(s3c2442_ffactor));
  352. break;
  353. }
  354. /*
  355. * Register common aliases at the end, as some of the aliased clocks
  356. * are SoC specific.
  357. */
  358. samsung_clk_register_alias(ctx, s3c2410_common_aliases,
  359. ARRAY_SIZE(s3c2410_common_aliases));
  360. if (current_soc == S3C2440 || current_soc == S3C2442) {
  361. samsung_clk_register_alias(ctx, s3c244x_common_aliases,
  362. ARRAY_SIZE(s3c244x_common_aliases));
  363. }
  364. samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
  365. ARRAY_SIZE(s3c2410_clk_regs));
  366. samsung_clk_of_add_provider(np, ctx);
  367. }
  368. static void __init s3c2410_clk_init(struct device_node *np)
  369. {
  370. s3c2410_common_clk_init(np, 0, S3C2410, NULL);
  371. }
  372. CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
  373. static void __init s3c2440_clk_init(struct device_node *np)
  374. {
  375. s3c2410_common_clk_init(np, 0, S3C2440, NULL);
  376. }
  377. CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
  378. static void __init s3c2442_clk_init(struct device_node *np)
  379. {
  380. s3c2410_common_clk_init(np, 0, S3C2442, NULL);
  381. }
  382. CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);