clk-s3c2410-dclk.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  4. *
  5. * Common Clock Framework support for s3c24xx external clock output.
  6. */
  7. #include <linux/clkdev.h>
  8. #include <linux/slab.h>
  9. #include <linux/clk.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/io.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/platform_data/clk-s3c2410.h>
  14. #include <linux/module.h>
  15. #include "clk.h"
  16. #define MUX_DCLK0 0
  17. #define MUX_DCLK1 1
  18. #define DIV_DCLK0 2
  19. #define DIV_DCLK1 3
  20. #define GATE_DCLK0 4
  21. #define GATE_DCLK1 5
  22. #define MUX_CLKOUT0 6
  23. #define MUX_CLKOUT1 7
  24. #define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
  25. enum supported_socs {
  26. S3C2410,
  27. S3C2412,
  28. S3C2440,
  29. S3C2443,
  30. };
  31. struct s3c24xx_dclk_drv_data {
  32. const char **clkout0_parent_names;
  33. int clkout0_num_parents;
  34. const char **clkout1_parent_names;
  35. int clkout1_num_parents;
  36. const char **mux_parent_names;
  37. int mux_num_parents;
  38. };
  39. /*
  40. * Clock for output-parent selection in misccr
  41. */
  42. struct s3c24xx_clkout {
  43. struct clk_hw hw;
  44. u32 mask;
  45. u8 shift;
  46. unsigned int (*modify_misccr)(unsigned int clr, unsigned int chg);
  47. };
  48. #define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
  49. static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
  50. {
  51. struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
  52. int num_parents = clk_hw_get_num_parents(hw);
  53. u32 val;
  54. val = clkout->modify_misccr(0, 0) >> clkout->shift;
  55. val >>= clkout->shift;
  56. val &= clkout->mask;
  57. if (val >= num_parents)
  58. return -EINVAL;
  59. return val;
  60. }
  61. static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
  62. {
  63. struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
  64. clkout->modify_misccr((clkout->mask << clkout->shift),
  65. (index << clkout->shift));
  66. return 0;
  67. }
  68. static const struct clk_ops s3c24xx_clkout_ops = {
  69. .get_parent = s3c24xx_clkout_get_parent,
  70. .set_parent = s3c24xx_clkout_set_parent,
  71. .determine_rate = __clk_mux_determine_rate,
  72. };
  73. static struct clk_hw *s3c24xx_register_clkout(struct device *dev,
  74. const char *name, const char **parent_names, u8 num_parents,
  75. u8 shift, u32 mask)
  76. {
  77. struct s3c2410_clk_platform_data *pdata = dev_get_platdata(dev);
  78. struct s3c24xx_clkout *clkout;
  79. struct clk_init_data init;
  80. int ret;
  81. if (!pdata)
  82. return ERR_PTR(-EINVAL);
  83. /* allocate the clkout */
  84. clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
  85. if (!clkout)
  86. return ERR_PTR(-ENOMEM);
  87. init.name = name;
  88. init.ops = &s3c24xx_clkout_ops;
  89. init.flags = 0;
  90. init.parent_names = parent_names;
  91. init.num_parents = num_parents;
  92. clkout->shift = shift;
  93. clkout->mask = mask;
  94. clkout->hw.init = &init;
  95. clkout->modify_misccr = pdata->modify_misccr;
  96. ret = clk_hw_register(dev, &clkout->hw);
  97. if (ret)
  98. return ERR_PTR(ret);
  99. return &clkout->hw;
  100. }
  101. /*
  102. * dclk and clkout init
  103. */
  104. struct s3c24xx_dclk {
  105. struct device *dev;
  106. void __iomem *base;
  107. struct notifier_block dclk0_div_change_nb;
  108. struct notifier_block dclk1_div_change_nb;
  109. spinlock_t dclk_lock;
  110. unsigned long reg_save;
  111. /* clk_data must be the last entry in the structure */
  112. struct clk_hw_onecell_data clk_data;
  113. };
  114. #define to_s3c24xx_dclk0(x) \
  115. container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
  116. #define to_s3c24xx_dclk1(x) \
  117. container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
  118. static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
  119. static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
  120. "gate_dclk0" };
  121. static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
  122. "gate_dclk1" };
  123. static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
  124. "hclk", "pclk", "gate_dclk0" };
  125. static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
  126. "gate_dclk1" };
  127. static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
  128. "gate_dclk0" };
  129. static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
  130. "hclk", "pclk", "gate_dclk1" };
  131. static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
  132. static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
  133. "gate_dclk0" };
  134. static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
  135. "hclk", "pclk", "gate_dclk1" };
  136. #define DCLKCON_DCLK_DIV_MASK 0xf
  137. #define DCLKCON_DCLK0_DIV_SHIFT 4
  138. #define DCLKCON_DCLK0_CMP_SHIFT 8
  139. #define DCLKCON_DCLK1_DIV_SHIFT 20
  140. #define DCLKCON_DCLK1_CMP_SHIFT 24
  141. static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
  142. int div_shift, int cmp_shift)
  143. {
  144. unsigned long flags = 0;
  145. u32 dclk_con, div, cmp;
  146. spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
  147. dclk_con = readl_relaxed(s3c24xx_dclk->base);
  148. div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
  149. cmp = ((div + 1) / 2) - 1;
  150. dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
  151. dclk_con |= (cmp << cmp_shift);
  152. writel_relaxed(dclk_con, s3c24xx_dclk->base);
  153. spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
  154. }
  155. static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
  156. unsigned long event, void *data)
  157. {
  158. struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
  159. if (event == POST_RATE_CHANGE) {
  160. s3c24xx_dclk_update_cmp(s3c24xx_dclk,
  161. DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
  162. }
  163. return NOTIFY_DONE;
  164. }
  165. static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
  166. unsigned long event, void *data)
  167. {
  168. struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
  169. if (event == POST_RATE_CHANGE) {
  170. s3c24xx_dclk_update_cmp(s3c24xx_dclk,
  171. DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
  172. }
  173. return NOTIFY_DONE;
  174. }
  175. #ifdef CONFIG_PM_SLEEP
  176. static int s3c24xx_dclk_suspend(struct device *dev)
  177. {
  178. struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
  179. s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
  180. return 0;
  181. }
  182. static int s3c24xx_dclk_resume(struct device *dev)
  183. {
  184. struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
  185. writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
  186. return 0;
  187. }
  188. #endif
  189. static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
  190. s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
  191. static int s3c24xx_dclk_probe(struct platform_device *pdev)
  192. {
  193. struct s3c24xx_dclk *s3c24xx_dclk;
  194. struct s3c24xx_dclk_drv_data *dclk_variant;
  195. struct clk_hw **clk_table;
  196. int ret, i;
  197. s3c24xx_dclk = devm_kzalloc(&pdev->dev,
  198. struct_size(s3c24xx_dclk, clk_data.hws,
  199. DCLK_MAX_CLKS),
  200. GFP_KERNEL);
  201. if (!s3c24xx_dclk)
  202. return -ENOMEM;
  203. clk_table = s3c24xx_dclk->clk_data.hws;
  204. s3c24xx_dclk->dev = &pdev->dev;
  205. s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
  206. platform_set_drvdata(pdev, s3c24xx_dclk);
  207. spin_lock_init(&s3c24xx_dclk->dclk_lock);
  208. s3c24xx_dclk->base = devm_platform_ioremap_resource(pdev, 0);
  209. if (IS_ERR(s3c24xx_dclk->base))
  210. return PTR_ERR(s3c24xx_dclk->base);
  211. dclk_variant = (struct s3c24xx_dclk_drv_data *)
  212. platform_get_device_id(pdev)->driver_data;
  213. clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
  214. dclk_variant->mux_parent_names,
  215. dclk_variant->mux_num_parents, 0,
  216. s3c24xx_dclk->base, 1, 1, 0,
  217. &s3c24xx_dclk->dclk_lock);
  218. clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
  219. dclk_variant->mux_parent_names,
  220. dclk_variant->mux_num_parents, 0,
  221. s3c24xx_dclk->base, 17, 1, 0,
  222. &s3c24xx_dclk->dclk_lock);
  223. clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
  224. "mux_dclk0", 0, s3c24xx_dclk->base,
  225. 4, 4, 0, &s3c24xx_dclk->dclk_lock);
  226. clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
  227. "mux_dclk1", 0, s3c24xx_dclk->base,
  228. 20, 4, 0, &s3c24xx_dclk->dclk_lock);
  229. clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
  230. "div_dclk0", CLK_SET_RATE_PARENT,
  231. s3c24xx_dclk->base, 0, 0,
  232. &s3c24xx_dclk->dclk_lock);
  233. clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
  234. "div_dclk1", CLK_SET_RATE_PARENT,
  235. s3c24xx_dclk->base, 16, 0,
  236. &s3c24xx_dclk->dclk_lock);
  237. clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
  238. "clkout0", dclk_variant->clkout0_parent_names,
  239. dclk_variant->clkout0_num_parents, 4, 7);
  240. clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
  241. "clkout1", dclk_variant->clkout1_parent_names,
  242. dclk_variant->clkout1_num_parents, 8, 7);
  243. for (i = 0; i < DCLK_MAX_CLKS; i++)
  244. if (IS_ERR(clk_table[i])) {
  245. dev_err(&pdev->dev, "clock %d failed to register\n", i);
  246. ret = PTR_ERR(clk_table[i]);
  247. goto err_clk_register;
  248. }
  249. ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
  250. if (!ret)
  251. ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
  252. NULL);
  253. if (!ret)
  254. ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
  255. "clkout0", NULL);
  256. if (!ret)
  257. ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
  258. "clkout1", NULL);
  259. if (ret) {
  260. dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
  261. goto err_clk_register;
  262. }
  263. s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
  264. s3c24xx_dclk0_div_notify;
  265. s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
  266. s3c24xx_dclk1_div_notify;
  267. ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
  268. &s3c24xx_dclk->dclk0_div_change_nb);
  269. if (ret)
  270. goto err_clk_register;
  271. ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
  272. &s3c24xx_dclk->dclk1_div_change_nb);
  273. if (ret)
  274. goto err_dclk_notify;
  275. return 0;
  276. err_dclk_notify:
  277. clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
  278. &s3c24xx_dclk->dclk0_div_change_nb);
  279. err_clk_register:
  280. for (i = 0; i < DCLK_MAX_CLKS; i++)
  281. if (clk_table[i] && !IS_ERR(clk_table[i]))
  282. clk_hw_unregister(clk_table[i]);
  283. return ret;
  284. }
  285. static int s3c24xx_dclk_remove(struct platform_device *pdev)
  286. {
  287. struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
  288. struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
  289. int i;
  290. clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
  291. &s3c24xx_dclk->dclk1_div_change_nb);
  292. clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
  293. &s3c24xx_dclk->dclk0_div_change_nb);
  294. for (i = 0; i < DCLK_MAX_CLKS; i++)
  295. clk_hw_unregister(clk_table[i]);
  296. return 0;
  297. }
  298. static struct s3c24xx_dclk_drv_data dclk_variants[] = {
  299. [S3C2410] = {
  300. .clkout0_parent_names = clkout0_s3c2410_p,
  301. .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
  302. .clkout1_parent_names = clkout1_s3c2410_p,
  303. .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
  304. .mux_parent_names = dclk_s3c2410_p,
  305. .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
  306. },
  307. [S3C2412] = {
  308. .clkout0_parent_names = clkout0_s3c2412_p,
  309. .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
  310. .clkout1_parent_names = clkout1_s3c2412_p,
  311. .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
  312. .mux_parent_names = dclk_s3c2410_p,
  313. .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
  314. },
  315. [S3C2440] = {
  316. .clkout0_parent_names = clkout0_s3c2440_p,
  317. .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
  318. .clkout1_parent_names = clkout1_s3c2440_p,
  319. .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
  320. .mux_parent_names = dclk_s3c2410_p,
  321. .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
  322. },
  323. [S3C2443] = {
  324. .clkout0_parent_names = clkout0_s3c2443_p,
  325. .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
  326. .clkout1_parent_names = clkout1_s3c2443_p,
  327. .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
  328. .mux_parent_names = dclk_s3c2443_p,
  329. .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
  330. },
  331. };
  332. static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
  333. {
  334. .name = "s3c2410-dclk",
  335. .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
  336. }, {
  337. .name = "s3c2412-dclk",
  338. .driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
  339. }, {
  340. .name = "s3c2440-dclk",
  341. .driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
  342. }, {
  343. .name = "s3c2443-dclk",
  344. .driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
  345. },
  346. { }
  347. };
  348. MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
  349. static struct platform_driver s3c24xx_dclk_driver = {
  350. .driver = {
  351. .name = "s3c24xx-dclk",
  352. .pm = &s3c24xx_dclk_pm_ops,
  353. .suppress_bind_attrs = true,
  354. },
  355. .probe = s3c24xx_dclk_probe,
  356. .remove = s3c24xx_dclk_remove,
  357. .id_table = s3c24xx_dclk_driver_ids,
  358. };
  359. module_platform_driver(s3c24xx_dclk_driver);
  360. MODULE_LICENSE("GPL v2");
  361. MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
  362. MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");