clk-pll.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. *
  6. * Common Clock Framework support for all PLL's in Samsung platforms
  7. */
  8. #ifndef __SAMSUNG_CLK_PLL_H
  9. #define __SAMSUNG_CLK_PLL_H
  10. enum samsung_pll_type {
  11. pll_2126,
  12. pll_3000,
  13. pll_35xx,
  14. pll_36xx,
  15. pll_2550,
  16. pll_2650,
  17. pll_4500,
  18. pll_4502,
  19. pll_4508,
  20. pll_4600,
  21. pll_4650,
  22. pll_4650c,
  23. pll_6552,
  24. pll_6552_s3c2416,
  25. pll_6553,
  26. pll_s3c2410_mpll,
  27. pll_s3c2410_upll,
  28. pll_s3c2440_mpll,
  29. pll_2550x,
  30. pll_2550xx,
  31. pll_2650x,
  32. pll_2650xx,
  33. pll_1450x,
  34. pll_1451x,
  35. pll_1452x,
  36. pll_1460x,
  37. };
  38. #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
  39. ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
  40. #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
  41. BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
  42. #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \
  43. { \
  44. .rate = PLL_VALID_RATE(_fin, _rate, \
  45. _m, _p, _s, 0, 16), \
  46. .mdiv = (_m), \
  47. .pdiv = (_p), \
  48. .sdiv = (_s), \
  49. }
  50. #define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s) \
  51. { \
  52. .rate = PLL_VALID_RATE(_fin, _rate, \
  53. _m + 8, _p + 2, _s, 0, 16), \
  54. .mdiv = (_m), \
  55. .pdiv = (_p), \
  56. .sdiv = (_s), \
  57. }
  58. #define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s) \
  59. { \
  60. .rate = PLL_VALID_RATE(_fin, _rate, \
  61. 2 * (_m + 8), _p + 2, _s, 0, 16), \
  62. .mdiv = (_m), \
  63. .pdiv = (_p), \
  64. .sdiv = (_s), \
  65. }
  66. #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \
  67. { \
  68. .rate = PLL_VALID_RATE(_fin, _rate, \
  69. _m, _p, _s, _k, 16), \
  70. .mdiv = (_m), \
  71. .pdiv = (_p), \
  72. .sdiv = (_s), \
  73. .kdiv = (_k), \
  74. }
  75. #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \
  76. { \
  77. .rate = PLL_VALID_RATE(_fin, _rate, \
  78. _m, _p, _s - 1, 0, 16), \
  79. .mdiv = (_m), \
  80. .pdiv = (_p), \
  81. .sdiv = (_s), \
  82. .afc = (_afc), \
  83. }
  84. #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \
  85. { \
  86. .rate = PLL_VALID_RATE(_fin, _rate, \
  87. _m, _p, _s, _k, 16), \
  88. .mdiv = (_m), \
  89. .pdiv = (_p), \
  90. .sdiv = (_s), \
  91. .kdiv = (_k), \
  92. .vsel = (_vsel), \
  93. }
  94. #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  95. { \
  96. .rate = PLL_VALID_RATE(_fin, _rate, \
  97. _m, _p, _s, _k, 10), \
  98. .mdiv = (_m), \
  99. .pdiv = (_p), \
  100. .sdiv = (_s), \
  101. .kdiv = (_k), \
  102. .mfr = (_mfr), \
  103. .mrr = (_mrr), \
  104. .vsel = (_vsel), \
  105. }
  106. /* NOTE: Rate table should be kept sorted in descending order. */
  107. struct samsung_pll_rate_table {
  108. unsigned int rate;
  109. unsigned int pdiv;
  110. unsigned int mdiv;
  111. unsigned int sdiv;
  112. unsigned int kdiv;
  113. unsigned int afc;
  114. unsigned int mfr;
  115. unsigned int mrr;
  116. unsigned int vsel;
  117. };
  118. #endif /* __SAMSUNG_CLK_PLL_H */