clk-exynos7.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  4. * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/of.h>
  8. #include "clk.h"
  9. #include <dt-bindings/clock/exynos7-clk.h>
  10. /* Register Offset definitions for CMU_TOPC (0x10570000) */
  11. #define CC_PLL_LOCK 0x0000
  12. #define BUS0_PLL_LOCK 0x0004
  13. #define BUS1_DPLL_LOCK 0x0008
  14. #define MFC_PLL_LOCK 0x000C
  15. #define AUD_PLL_LOCK 0x0010
  16. #define CC_PLL_CON0 0x0100
  17. #define BUS0_PLL_CON0 0x0110
  18. #define BUS1_DPLL_CON0 0x0120
  19. #define MFC_PLL_CON0 0x0130
  20. #define AUD_PLL_CON0 0x0140
  21. #define MUX_SEL_TOPC0 0x0200
  22. #define MUX_SEL_TOPC1 0x0204
  23. #define MUX_SEL_TOPC2 0x0208
  24. #define MUX_SEL_TOPC3 0x020C
  25. #define DIV_TOPC0 0x0600
  26. #define DIV_TOPC1 0x0604
  27. #define DIV_TOPC3 0x060C
  28. #define ENABLE_ACLK_TOPC0 0x0800
  29. #define ENABLE_ACLK_TOPC1 0x0804
  30. #define ENABLE_SCLK_TOPC1 0x0A04
  31. static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
  32. FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
  33. FFACTOR(0, "ffac_topc_bus0_pll_div4",
  34. "ffac_topc_bus0_pll_div2", 1, 2, 0),
  35. FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
  36. FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
  37. FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
  38. };
  39. /* List of parent clocks for Muxes in CMU_TOPC */
  40. PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
  41. PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
  42. PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
  43. PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
  44. PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
  45. PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
  46. "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
  47. "mout_topc_mfc_pll_half" };
  48. PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
  49. "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
  50. PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
  51. "ffac_topc_bus1_pll_div2"};
  52. PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
  53. "ffac_topc_cc_pll_div2"};
  54. PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
  55. "ffac_topc_mfc_pll_div2"};
  56. PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
  57. "ffac_topc_bus0_pll_div2"};
  58. static const unsigned long topc_clk_regs[] __initconst = {
  59. CC_PLL_LOCK,
  60. BUS0_PLL_LOCK,
  61. BUS1_DPLL_LOCK,
  62. MFC_PLL_LOCK,
  63. AUD_PLL_LOCK,
  64. CC_PLL_CON0,
  65. BUS0_PLL_CON0,
  66. BUS1_DPLL_CON0,
  67. MFC_PLL_CON0,
  68. AUD_PLL_CON0,
  69. MUX_SEL_TOPC0,
  70. MUX_SEL_TOPC1,
  71. MUX_SEL_TOPC2,
  72. MUX_SEL_TOPC3,
  73. DIV_TOPC0,
  74. DIV_TOPC1,
  75. DIV_TOPC3,
  76. };
  77. static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
  78. MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
  79. MUX_SEL_TOPC0, 0, 1),
  80. MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
  81. MUX_SEL_TOPC0, 4, 1),
  82. MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
  83. MUX_SEL_TOPC0, 8, 1),
  84. MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
  85. MUX_SEL_TOPC0, 12, 1),
  86. MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
  87. MUX_SEL_TOPC0, 16, 2),
  88. MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
  89. MUX_SEL_TOPC0, 20, 1),
  90. MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
  91. MUX_SEL_TOPC0, 24, 1),
  92. MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
  93. MUX_SEL_TOPC0, 28, 1),
  94. MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
  95. MUX_SEL_TOPC1, 0, 1),
  96. MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
  97. MUX_SEL_TOPC1, 16, 1),
  98. MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
  99. MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
  100. MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
  101. };
  102. static const struct samsung_div_clock topc_div_clks[] __initconst = {
  103. DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
  104. DIV_TOPC0, 4, 4),
  105. DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
  106. DIV_TOPC1, 20, 4),
  107. DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
  108. DIV_TOPC1, 24, 4),
  109. DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
  110. DIV_TOPC3, 0, 4),
  111. DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
  112. DIV_TOPC3, 8, 4),
  113. DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
  114. DIV_TOPC3, 12, 4),
  115. DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
  116. DIV_TOPC3, 16, 4),
  117. DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
  118. DIV_TOPC3, 28, 4),
  119. };
  120. static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
  121. PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
  122. {},
  123. };
  124. static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
  125. GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
  126. ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
  127. GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
  128. ENABLE_ACLK_TOPC1, 20, 0, 0),
  129. GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
  130. ENABLE_ACLK_TOPC1, 24, 0, 0),
  131. GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
  132. ENABLE_SCLK_TOPC1, 20, 0, 0),
  133. GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
  134. ENABLE_SCLK_TOPC1, 17, 0, 0),
  135. GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
  136. ENABLE_SCLK_TOPC1, 16, 0, 0),
  137. GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
  138. ENABLE_SCLK_TOPC1, 13, 0, 0),
  139. GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
  140. ENABLE_SCLK_TOPC1, 12, 0, 0),
  141. GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
  142. ENABLE_SCLK_TOPC1, 5, 0, 0),
  143. GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
  144. ENABLE_SCLK_TOPC1, 4, 0, 0),
  145. GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
  146. ENABLE_SCLK_TOPC1, 1, 0, 0),
  147. GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
  148. ENABLE_SCLK_TOPC1, 0, 0, 0),
  149. };
  150. static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
  151. PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
  152. BUS0_PLL_CON0, NULL),
  153. PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
  154. CC_PLL_CON0, NULL),
  155. PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
  156. BUS1_DPLL_CON0, NULL),
  157. PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
  158. MFC_PLL_CON0, NULL),
  159. PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
  160. AUD_PLL_CON0, pll1460x_24mhz_tbl),
  161. };
  162. static const struct samsung_cmu_info topc_cmu_info __initconst = {
  163. .pll_clks = topc_pll_clks,
  164. .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
  165. .mux_clks = topc_mux_clks,
  166. .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
  167. .div_clks = topc_div_clks,
  168. .nr_div_clks = ARRAY_SIZE(topc_div_clks),
  169. .gate_clks = topc_gate_clks,
  170. .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
  171. .fixed_factor_clks = topc_fixed_factor_clks,
  172. .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
  173. .nr_clk_ids = TOPC_NR_CLK,
  174. .clk_regs = topc_clk_regs,
  175. .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
  176. };
  177. static void __init exynos7_clk_topc_init(struct device_node *np)
  178. {
  179. samsung_cmu_register_one(np, &topc_cmu_info);
  180. }
  181. CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
  182. exynos7_clk_topc_init);
  183. /* Register Offset definitions for CMU_TOP0 (0x105D0000) */
  184. #define MUX_SEL_TOP00 0x0200
  185. #define MUX_SEL_TOP01 0x0204
  186. #define MUX_SEL_TOP03 0x020C
  187. #define MUX_SEL_TOP0_PERIC0 0x0230
  188. #define MUX_SEL_TOP0_PERIC1 0x0234
  189. #define MUX_SEL_TOP0_PERIC2 0x0238
  190. #define MUX_SEL_TOP0_PERIC3 0x023C
  191. #define DIV_TOP03 0x060C
  192. #define DIV_TOP0_PERIC0 0x0630
  193. #define DIV_TOP0_PERIC1 0x0634
  194. #define DIV_TOP0_PERIC2 0x0638
  195. #define DIV_TOP0_PERIC3 0x063C
  196. #define ENABLE_ACLK_TOP03 0x080C
  197. #define ENABLE_SCLK_TOP0_PERIC0 0x0A30
  198. #define ENABLE_SCLK_TOP0_PERIC1 0x0A34
  199. #define ENABLE_SCLK_TOP0_PERIC2 0x0A38
  200. #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
  201. /* List of parent clocks for Muxes in CMU_TOP0 */
  202. PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" };
  203. PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" };
  204. PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" };
  205. PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
  206. PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
  207. PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
  208. "ffac_top0_bus0_pll_div2"};
  209. PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
  210. "ffac_top0_bus1_pll_div2"};
  211. PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
  212. "ffac_top0_cc_pll_div2"};
  213. PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
  214. "ffac_top0_mfc_pll_div2"};
  215. PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
  216. "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
  217. "mout_top0_mfc_pll_half"};
  218. PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
  219. "ioclk_audiocdclk1", "ioclk_spdif_extclk",
  220. "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
  221. "mout_top0_bus1_pll_half"};
  222. PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
  223. "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
  224. static const unsigned long top0_clk_regs[] __initconst = {
  225. MUX_SEL_TOP00,
  226. MUX_SEL_TOP01,
  227. MUX_SEL_TOP03,
  228. MUX_SEL_TOP0_PERIC0,
  229. MUX_SEL_TOP0_PERIC1,
  230. MUX_SEL_TOP0_PERIC2,
  231. MUX_SEL_TOP0_PERIC3,
  232. DIV_TOP03,
  233. DIV_TOP0_PERIC0,
  234. DIV_TOP0_PERIC1,
  235. DIV_TOP0_PERIC2,
  236. DIV_TOP0_PERIC3,
  237. ENABLE_SCLK_TOP0_PERIC0,
  238. ENABLE_SCLK_TOP0_PERIC1,
  239. ENABLE_SCLK_TOP0_PERIC2,
  240. ENABLE_SCLK_TOP0_PERIC3,
  241. };
  242. static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
  243. MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
  244. MUX_SEL_TOP00, 0, 1),
  245. MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
  246. MUX_SEL_TOP00, 4, 1),
  247. MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
  248. MUX_SEL_TOP00, 8, 1),
  249. MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
  250. MUX_SEL_TOP00, 12, 1),
  251. MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
  252. MUX_SEL_TOP00, 16, 1),
  253. MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
  254. MUX_SEL_TOP01, 4, 1),
  255. MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
  256. MUX_SEL_TOP01, 8, 1),
  257. MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
  258. MUX_SEL_TOP01, 12, 1),
  259. MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
  260. MUX_SEL_TOP01, 16, 1),
  261. MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
  262. MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
  263. MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
  264. MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
  265. MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
  266. MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
  267. MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
  268. MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
  269. MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
  270. MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
  271. MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
  272. MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
  273. MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
  274. MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
  275. };
  276. static const struct samsung_div_clock top0_div_clks[] __initconst = {
  277. DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
  278. DIV_TOP03, 12, 6),
  279. DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
  280. DIV_TOP03, 20, 6),
  281. DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
  282. DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
  283. DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
  284. DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
  285. DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
  286. DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
  287. DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
  288. DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
  289. DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
  290. DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
  291. DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
  292. DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
  293. };
  294. static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
  295. GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
  296. ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
  297. GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
  298. ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
  299. GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
  300. ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
  301. GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
  302. ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
  303. GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
  304. ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
  305. GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
  306. ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
  307. GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
  308. ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
  309. GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
  310. ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
  311. GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
  312. ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
  313. GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
  314. ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
  315. GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
  316. ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
  317. GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
  318. ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
  319. GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
  320. ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
  321. GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
  322. ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
  323. };
  324. static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
  325. FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
  326. 1, 2, 0),
  327. FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
  328. 1, 2, 0),
  329. FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
  330. FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
  331. };
  332. static const struct samsung_cmu_info top0_cmu_info __initconst = {
  333. .mux_clks = top0_mux_clks,
  334. .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
  335. .div_clks = top0_div_clks,
  336. .nr_div_clks = ARRAY_SIZE(top0_div_clks),
  337. .gate_clks = top0_gate_clks,
  338. .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
  339. .fixed_factor_clks = top0_fixed_factor_clks,
  340. .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
  341. .nr_clk_ids = TOP0_NR_CLK,
  342. .clk_regs = top0_clk_regs,
  343. .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
  344. };
  345. static void __init exynos7_clk_top0_init(struct device_node *np)
  346. {
  347. samsung_cmu_register_one(np, &top0_cmu_info);
  348. }
  349. CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
  350. exynos7_clk_top0_init);
  351. /* Register Offset definitions for CMU_TOP1 (0x105E0000) */
  352. #define MUX_SEL_TOP10 0x0200
  353. #define MUX_SEL_TOP11 0x0204
  354. #define MUX_SEL_TOP13 0x020C
  355. #define MUX_SEL_TOP1_FSYS0 0x0224
  356. #define MUX_SEL_TOP1_FSYS1 0x0228
  357. #define MUX_SEL_TOP1_FSYS11 0x022C
  358. #define DIV_TOP13 0x060C
  359. #define DIV_TOP1_FSYS0 0x0624
  360. #define DIV_TOP1_FSYS1 0x0628
  361. #define DIV_TOP1_FSYS11 0x062C
  362. #define ENABLE_ACLK_TOP13 0x080C
  363. #define ENABLE_SCLK_TOP1_FSYS0 0x0A24
  364. #define ENABLE_SCLK_TOP1_FSYS1 0x0A28
  365. #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
  366. /* List of parent clocks for Muxes in CMU_TOP1 */
  367. PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" };
  368. PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" };
  369. PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" };
  370. PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
  371. PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
  372. "ffac_top1_bus0_pll_div2"};
  373. PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
  374. "ffac_top1_bus1_pll_div2"};
  375. PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
  376. "ffac_top1_cc_pll_div2"};
  377. PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
  378. "ffac_top1_mfc_pll_div2"};
  379. PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
  380. "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
  381. "mout_top1_mfc_pll_half"};
  382. static const unsigned long top1_clk_regs[] __initconst = {
  383. MUX_SEL_TOP10,
  384. MUX_SEL_TOP11,
  385. MUX_SEL_TOP13,
  386. MUX_SEL_TOP1_FSYS0,
  387. MUX_SEL_TOP1_FSYS1,
  388. MUX_SEL_TOP1_FSYS11,
  389. DIV_TOP13,
  390. DIV_TOP1_FSYS0,
  391. DIV_TOP1_FSYS1,
  392. DIV_TOP1_FSYS11,
  393. ENABLE_ACLK_TOP13,
  394. ENABLE_SCLK_TOP1_FSYS0,
  395. ENABLE_SCLK_TOP1_FSYS1,
  396. ENABLE_SCLK_TOP1_FSYS11,
  397. };
  398. static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
  399. MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
  400. MUX_SEL_TOP10, 4, 1),
  401. MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
  402. MUX_SEL_TOP10, 8, 1),
  403. MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
  404. MUX_SEL_TOP10, 12, 1),
  405. MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
  406. MUX_SEL_TOP10, 16, 1),
  407. MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
  408. MUX_SEL_TOP11, 4, 1),
  409. MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
  410. MUX_SEL_TOP11, 8, 1),
  411. MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
  412. MUX_SEL_TOP11, 12, 1),
  413. MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
  414. MUX_SEL_TOP11, 16, 1),
  415. MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
  416. MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
  417. MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
  418. MUX_SEL_TOP1_FSYS0, 0, 2),
  419. MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
  420. MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
  421. MUX_SEL_TOP1_FSYS0, 28, 2),
  422. MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
  423. MUX_SEL_TOP1_FSYS1, 0, 2),
  424. MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
  425. MUX_SEL_TOP1_FSYS1, 16, 2),
  426. MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
  427. MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
  428. MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
  429. MUX_SEL_TOP1_FSYS11, 24, 2),
  430. };
  431. static const struct samsung_div_clock top1_div_clks[] __initconst = {
  432. DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
  433. DIV_TOP13, 24, 4),
  434. DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
  435. DIV_TOP13, 28, 4),
  436. DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
  437. "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
  438. DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
  439. "mout_sclk_ufsunipro20",
  440. DIV_TOP1_FSYS1, 16, 6),
  441. DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
  442. DIV_TOP1_FSYS0, 16, 10),
  443. DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
  444. DIV_TOP1_FSYS0, 28, 4),
  445. DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
  446. DIV_TOP1_FSYS11, 0, 10),
  447. DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
  448. DIV_TOP1_FSYS11, 12, 10),
  449. DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
  450. "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
  451. };
  452. static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
  453. GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
  454. ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
  455. GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
  456. ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
  457. GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
  458. ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
  459. GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
  460. ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
  461. GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
  462. ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
  463. GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
  464. ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
  465. GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
  466. ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
  467. CLK_IS_CRITICAL, 0),
  468. /*
  469. * This clock is required for the CMU_FSYS1 registers access, keep it
  470. * enabled permanently until proper runtime PM support is added.
  471. */
  472. GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
  473. ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
  474. CLK_IS_CRITICAL, 0),
  475. GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
  476. "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
  477. 24, CLK_SET_RATE_PARENT, 0),
  478. };
  479. static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
  480. FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
  481. 1, 2, 0),
  482. FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
  483. 1, 2, 0),
  484. FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
  485. FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
  486. };
  487. static const struct samsung_cmu_info top1_cmu_info __initconst = {
  488. .mux_clks = top1_mux_clks,
  489. .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
  490. .div_clks = top1_div_clks,
  491. .nr_div_clks = ARRAY_SIZE(top1_div_clks),
  492. .gate_clks = top1_gate_clks,
  493. .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
  494. .fixed_factor_clks = top1_fixed_factor_clks,
  495. .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
  496. .nr_clk_ids = TOP1_NR_CLK,
  497. .clk_regs = top1_clk_regs,
  498. .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
  499. };
  500. static void __init exynos7_clk_top1_init(struct device_node *np)
  501. {
  502. samsung_cmu_register_one(np, &top1_cmu_info);
  503. }
  504. CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
  505. exynos7_clk_top1_init);
  506. /* Register Offset definitions for CMU_CCORE (0x105B0000) */
  507. #define MUX_SEL_CCORE 0x0200
  508. #define DIV_CCORE 0x0600
  509. #define ENABLE_ACLK_CCORE0 0x0800
  510. #define ENABLE_ACLK_CCORE1 0x0804
  511. #define ENABLE_PCLK_CCORE 0x0900
  512. /*
  513. * List of parent clocks for Muxes in CMU_CCORE
  514. */
  515. PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
  516. static const unsigned long ccore_clk_regs[] __initconst = {
  517. MUX_SEL_CCORE,
  518. ENABLE_PCLK_CCORE,
  519. };
  520. static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
  521. MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
  522. MUX_SEL_CCORE, 1, 1),
  523. };
  524. static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
  525. GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
  526. ENABLE_PCLK_CCORE, 8, 0, 0),
  527. };
  528. static const struct samsung_cmu_info ccore_cmu_info __initconst = {
  529. .mux_clks = ccore_mux_clks,
  530. .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
  531. .gate_clks = ccore_gate_clks,
  532. .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
  533. .nr_clk_ids = CCORE_NR_CLK,
  534. .clk_regs = ccore_clk_regs,
  535. .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
  536. };
  537. static void __init exynos7_clk_ccore_init(struct device_node *np)
  538. {
  539. samsung_cmu_register_one(np, &ccore_cmu_info);
  540. }
  541. CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
  542. exynos7_clk_ccore_init);
  543. /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
  544. #define MUX_SEL_PERIC0 0x0200
  545. #define ENABLE_PCLK_PERIC0 0x0900
  546. #define ENABLE_SCLK_PERIC0 0x0A00
  547. /* List of parent clocks for Muxes in CMU_PERIC0 */
  548. PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
  549. PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
  550. static const unsigned long peric0_clk_regs[] __initconst = {
  551. MUX_SEL_PERIC0,
  552. ENABLE_PCLK_PERIC0,
  553. ENABLE_SCLK_PERIC0,
  554. };
  555. static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
  556. MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
  557. MUX_SEL_PERIC0, 0, 1),
  558. MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
  559. MUX_SEL_PERIC0, 16, 1),
  560. };
  561. static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
  562. GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
  563. ENABLE_PCLK_PERIC0, 8, 0, 0),
  564. GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
  565. ENABLE_PCLK_PERIC0, 9, 0, 0),
  566. GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
  567. ENABLE_PCLK_PERIC0, 10, 0, 0),
  568. GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
  569. ENABLE_PCLK_PERIC0, 11, 0, 0),
  570. GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
  571. ENABLE_PCLK_PERIC0, 12, 0, 0),
  572. GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
  573. ENABLE_PCLK_PERIC0, 13, 0, 0),
  574. GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
  575. ENABLE_PCLK_PERIC0, 14, 0, 0),
  576. GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
  577. ENABLE_PCLK_PERIC0, 16, 0, 0),
  578. GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
  579. ENABLE_PCLK_PERIC0, 20, 0, 0),
  580. GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
  581. ENABLE_PCLK_PERIC0, 21, 0, 0),
  582. GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
  583. ENABLE_SCLK_PERIC0, 16, 0, 0),
  584. GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
  585. };
  586. static const struct samsung_cmu_info peric0_cmu_info __initconst = {
  587. .mux_clks = peric0_mux_clks,
  588. .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
  589. .gate_clks = peric0_gate_clks,
  590. .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
  591. .nr_clk_ids = PERIC0_NR_CLK,
  592. .clk_regs = peric0_clk_regs,
  593. .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
  594. };
  595. static void __init exynos7_clk_peric0_init(struct device_node *np)
  596. {
  597. samsung_cmu_register_one(np, &peric0_cmu_info);
  598. }
  599. /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
  600. #define MUX_SEL_PERIC10 0x0200
  601. #define MUX_SEL_PERIC11 0x0204
  602. #define MUX_SEL_PERIC12 0x0208
  603. #define ENABLE_PCLK_PERIC1 0x0900
  604. #define ENABLE_SCLK_PERIC10 0x0A00
  605. CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
  606. exynos7_clk_peric0_init);
  607. /* List of parent clocks for Muxes in CMU_PERIC1 */
  608. PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
  609. PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
  610. PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
  611. PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
  612. PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
  613. PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
  614. PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
  615. PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
  616. PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
  617. static const unsigned long peric1_clk_regs[] __initconst = {
  618. MUX_SEL_PERIC10,
  619. MUX_SEL_PERIC11,
  620. MUX_SEL_PERIC12,
  621. ENABLE_PCLK_PERIC1,
  622. ENABLE_SCLK_PERIC10,
  623. };
  624. static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
  625. MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
  626. MUX_SEL_PERIC10, 0, 1),
  627. MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
  628. MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
  629. MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
  630. MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
  631. MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
  632. MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
  633. MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
  634. MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
  635. MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
  636. MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
  637. MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
  638. MUX_SEL_PERIC11, 20, 1),
  639. MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
  640. MUX_SEL_PERIC11, 24, 1),
  641. MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
  642. MUX_SEL_PERIC11, 28, 1),
  643. };
  644. static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
  645. GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
  646. ENABLE_PCLK_PERIC1, 4, 0, 0),
  647. GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
  648. ENABLE_PCLK_PERIC1, 5, 0, 0),
  649. GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
  650. ENABLE_PCLK_PERIC1, 6, 0, 0),
  651. GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
  652. ENABLE_PCLK_PERIC1, 7, 0, 0),
  653. GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
  654. ENABLE_PCLK_PERIC1, 8, 0, 0),
  655. GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
  656. ENABLE_PCLK_PERIC1, 9, 0, 0),
  657. GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
  658. ENABLE_PCLK_PERIC1, 10, 0, 0),
  659. GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
  660. ENABLE_PCLK_PERIC1, 11, 0, 0),
  661. GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
  662. ENABLE_PCLK_PERIC1, 12, 0, 0),
  663. GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
  664. ENABLE_PCLK_PERIC1, 13, 0, 0),
  665. GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
  666. ENABLE_PCLK_PERIC1, 14, 0, 0),
  667. GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
  668. ENABLE_PCLK_PERIC1, 15, 0, 0),
  669. GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
  670. ENABLE_PCLK_PERIC1, 16, 0, 0),
  671. GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
  672. ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
  673. GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
  674. ENABLE_PCLK_PERIC1, 18, 0, 0),
  675. GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
  676. ENABLE_PCLK_PERIC1, 19, 0, 0),
  677. GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
  678. ENABLE_SCLK_PERIC10, 9, 0, 0),
  679. GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
  680. ENABLE_SCLK_PERIC10, 10, 0, 0),
  681. GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
  682. ENABLE_SCLK_PERIC10, 11, 0, 0),
  683. GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
  684. ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
  685. GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
  686. ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
  687. GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
  688. ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
  689. GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
  690. ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
  691. GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
  692. ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
  693. GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
  694. ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
  695. GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
  696. ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
  697. GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
  698. ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
  699. };
  700. static const struct samsung_cmu_info peric1_cmu_info __initconst = {
  701. .mux_clks = peric1_mux_clks,
  702. .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
  703. .gate_clks = peric1_gate_clks,
  704. .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
  705. .nr_clk_ids = PERIC1_NR_CLK,
  706. .clk_regs = peric1_clk_regs,
  707. .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
  708. };
  709. static void __init exynos7_clk_peric1_init(struct device_node *np)
  710. {
  711. samsung_cmu_register_one(np, &peric1_cmu_info);
  712. }
  713. CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
  714. exynos7_clk_peric1_init);
  715. /* Register Offset definitions for CMU_PERIS (0x10040000) */
  716. #define MUX_SEL_PERIS 0x0200
  717. #define ENABLE_PCLK_PERIS 0x0900
  718. #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
  719. #define ENABLE_SCLK_PERIS 0x0A00
  720. #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
  721. /* List of parent clocks for Muxes in CMU_PERIS */
  722. PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
  723. static const unsigned long peris_clk_regs[] __initconst = {
  724. MUX_SEL_PERIS,
  725. ENABLE_PCLK_PERIS,
  726. ENABLE_PCLK_PERIS_SECURE_CHIPID,
  727. ENABLE_SCLK_PERIS,
  728. ENABLE_SCLK_PERIS_SECURE_CHIPID,
  729. };
  730. static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
  731. MUX(0, "mout_aclk_peris_66_user",
  732. mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
  733. };
  734. static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
  735. GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
  736. ENABLE_PCLK_PERIS, 6, 0, 0),
  737. GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
  738. ENABLE_PCLK_PERIS, 10, 0, 0),
  739. GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
  740. ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
  741. GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
  742. ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
  743. GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
  744. };
  745. static const struct samsung_cmu_info peris_cmu_info __initconst = {
  746. .mux_clks = peris_mux_clks,
  747. .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
  748. .gate_clks = peris_gate_clks,
  749. .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
  750. .nr_clk_ids = PERIS_NR_CLK,
  751. .clk_regs = peris_clk_regs,
  752. .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
  753. };
  754. static void __init exynos7_clk_peris_init(struct device_node *np)
  755. {
  756. samsung_cmu_register_one(np, &peris_cmu_info);
  757. }
  758. CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
  759. exynos7_clk_peris_init);
  760. /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
  761. #define MUX_SEL_FSYS00 0x0200
  762. #define MUX_SEL_FSYS01 0x0204
  763. #define MUX_SEL_FSYS02 0x0208
  764. #define ENABLE_ACLK_FSYS00 0x0800
  765. #define ENABLE_ACLK_FSYS01 0x0804
  766. #define ENABLE_SCLK_FSYS01 0x0A04
  767. #define ENABLE_SCLK_FSYS02 0x0A08
  768. #define ENABLE_SCLK_FSYS04 0x0A10
  769. /*
  770. * List of parent clocks for Muxes in CMU_FSYS0
  771. */
  772. PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" };
  773. PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" };
  774. PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" };
  775. PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll",
  776. "phyclk_usbdrd300_udrd30_phyclock" };
  777. PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
  778. "phyclk_usbdrd300_udrd30_pipe_pclk" };
  779. /* fixed rate clocks used in the FSYS0 block */
  780. static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
  781. FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
  782. FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
  783. };
  784. static const unsigned long fsys0_clk_regs[] __initconst = {
  785. MUX_SEL_FSYS00,
  786. MUX_SEL_FSYS01,
  787. MUX_SEL_FSYS02,
  788. ENABLE_ACLK_FSYS00,
  789. ENABLE_ACLK_FSYS01,
  790. ENABLE_SCLK_FSYS01,
  791. ENABLE_SCLK_FSYS02,
  792. ENABLE_SCLK_FSYS04,
  793. };
  794. static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
  795. MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
  796. MUX_SEL_FSYS00, 24, 1),
  797. MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
  798. MUX_SEL_FSYS01, 24, 1),
  799. MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
  800. MUX_SEL_FSYS01, 28, 1),
  801. MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
  802. mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
  803. MUX_SEL_FSYS02, 24, 1),
  804. MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
  805. mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
  806. MUX_SEL_FSYS02, 28, 1),
  807. };
  808. static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
  809. GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
  810. ENABLE_ACLK_FSYS00, 3, 0, 0),
  811. GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
  812. ENABLE_ACLK_FSYS00, 4, 0, 0),
  813. GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
  814. "mout_aclk_fsys0_200_user",
  815. ENABLE_ACLK_FSYS00, 19, 0, 0),
  816. GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
  817. ENABLE_ACLK_FSYS01, 29, 0, 0),
  818. GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
  819. ENABLE_ACLK_FSYS01, 31, 0, 0),
  820. GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
  821. "mout_sclk_usbdrd300_user",
  822. ENABLE_SCLK_FSYS01, 4, 0, 0),
  823. GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
  824. ENABLE_SCLK_FSYS01, 8, 0, 0),
  825. GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
  826. "phyclk_usbdrd300_udrd30_pipe_pclk_user",
  827. "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
  828. ENABLE_SCLK_FSYS02, 24, 0, 0),
  829. GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
  830. "phyclk_usbdrd300_udrd30_phyclk_user",
  831. "mout_phyclk_usbdrd300_udrd30_phyclk_user",
  832. ENABLE_SCLK_FSYS02, 28, 0, 0),
  833. GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
  834. "fin_pll",
  835. ENABLE_SCLK_FSYS04, 28, 0, 0),
  836. };
  837. static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
  838. .fixed_clks = fixed_rate_clks_fsys0,
  839. .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
  840. .mux_clks = fsys0_mux_clks,
  841. .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
  842. .gate_clks = fsys0_gate_clks,
  843. .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
  844. .nr_clk_ids = FSYS0_NR_CLK,
  845. .clk_regs = fsys0_clk_regs,
  846. .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
  847. };
  848. static void __init exynos7_clk_fsys0_init(struct device_node *np)
  849. {
  850. samsung_cmu_register_one(np, &fsys0_cmu_info);
  851. }
  852. CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
  853. exynos7_clk_fsys0_init);
  854. /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
  855. #define MUX_SEL_FSYS10 0x0200
  856. #define MUX_SEL_FSYS11 0x0204
  857. #define MUX_SEL_FSYS12 0x0208
  858. #define DIV_FSYS1 0x0600
  859. #define ENABLE_ACLK_FSYS1 0x0800
  860. #define ENABLE_PCLK_FSYS1 0x0900
  861. #define ENABLE_SCLK_FSYS11 0x0A04
  862. #define ENABLE_SCLK_FSYS12 0x0A08
  863. #define ENABLE_SCLK_FSYS13 0x0A0C
  864. /*
  865. * List of parent clocks for Muxes in CMU_FSYS1
  866. */
  867. PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
  868. PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m",
  869. "sclk_phy_fsys1_26m" };
  870. PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
  871. PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
  872. PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" };
  873. PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
  874. PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
  875. PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
  876. /* fixed rate clocks used in the FSYS1 block */
  877. static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
  878. FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
  879. 0, 300000000),
  880. FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
  881. 0, 300000000),
  882. FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
  883. 0, 300000000),
  884. };
  885. static const unsigned long fsys1_clk_regs[] __initconst = {
  886. MUX_SEL_FSYS10,
  887. MUX_SEL_FSYS11,
  888. MUX_SEL_FSYS12,
  889. DIV_FSYS1,
  890. ENABLE_ACLK_FSYS1,
  891. ENABLE_PCLK_FSYS1,
  892. ENABLE_SCLK_FSYS11,
  893. ENABLE_SCLK_FSYS12,
  894. ENABLE_SCLK_FSYS13,
  895. };
  896. static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
  897. MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
  898. mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
  899. MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
  900. MUX_SEL_FSYS10, 20, 2),
  901. MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
  902. MUX_SEL_FSYS10, 28, 1),
  903. MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
  904. MUX_SEL_FSYS11, 24, 1),
  905. MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
  906. MUX_SEL_FSYS11, 28, 1),
  907. MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
  908. MUX_SEL_FSYS11, 20, 1),
  909. MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
  910. mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
  911. MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
  912. mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
  913. MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
  914. mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
  915. };
  916. static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
  917. DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
  918. DIV_FSYS1, 0, 2),
  919. };
  920. static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
  921. GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
  922. "mout_sclk_ufsunipro20_user",
  923. ENABLE_SCLK_FSYS11, 20, 0, 0),
  924. GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
  925. ENABLE_ACLK_FSYS1, 29, 0, 0),
  926. GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
  927. ENABLE_ACLK_FSYS1, 30, 0, 0),
  928. GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
  929. ENABLE_ACLK_FSYS1, 31, 0, 0),
  930. GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
  931. ENABLE_PCLK_FSYS1, 30, 0, 0),
  932. GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
  933. "mout_phyclk_ufs20_rx1_symbol_user",
  934. ENABLE_SCLK_FSYS12, 16, 0, 0),
  935. GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
  936. "mout_phyclk_ufs20_rx0_symbol_user",
  937. ENABLE_SCLK_FSYS12, 24, 0, 0),
  938. GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
  939. "mout_phyclk_ufs20_tx0_symbol_user",
  940. ENABLE_SCLK_FSYS12, 28, 0, 0),
  941. GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
  942. "oscclk_phy_clkout_embedded_combo_phy",
  943. "fin_pll",
  944. ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
  945. GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
  946. "mout_fsys1_phyclk_sel1",
  947. ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
  948. };
  949. static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
  950. .fixed_clks = fixed_rate_clks_fsys1,
  951. .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
  952. .mux_clks = fsys1_mux_clks,
  953. .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
  954. .div_clks = fsys1_div_clks,
  955. .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
  956. .gate_clks = fsys1_gate_clks,
  957. .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
  958. .nr_clk_ids = FSYS1_NR_CLK,
  959. .clk_regs = fsys1_clk_regs,
  960. .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
  961. };
  962. static void __init exynos7_clk_fsys1_init(struct device_node *np)
  963. {
  964. samsung_cmu_register_one(np, &fsys1_cmu_info);
  965. }
  966. CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
  967. exynos7_clk_fsys1_init);
  968. #define MUX_SEL_MSCL 0x0200
  969. #define DIV_MSCL 0x0600
  970. #define ENABLE_ACLK_MSCL 0x0800
  971. #define ENABLE_PCLK_MSCL 0x0900
  972. /* List of parent clocks for Muxes in CMU_MSCL */
  973. PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
  974. static const unsigned long mscl_clk_regs[] __initconst = {
  975. MUX_SEL_MSCL,
  976. DIV_MSCL,
  977. ENABLE_ACLK_MSCL,
  978. ENABLE_PCLK_MSCL,
  979. };
  980. static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
  981. MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
  982. mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
  983. };
  984. static const struct samsung_div_clock mscl_div_clks[] __initconst = {
  985. DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
  986. DIV_MSCL, 0, 3),
  987. };
  988. static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
  989. GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
  990. ENABLE_ACLK_MSCL, 31, 0, 0),
  991. GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
  992. ENABLE_ACLK_MSCL, 30, 0, 0),
  993. GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
  994. ENABLE_ACLK_MSCL, 29, 0, 0),
  995. GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
  996. ENABLE_ACLK_MSCL, 28, 0, 0),
  997. GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
  998. "usermux_aclk_mscl_532",
  999. ENABLE_ACLK_MSCL, 27, 0, 0),
  1000. GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
  1001. "usermux_aclk_mscl_532",
  1002. ENABLE_ACLK_MSCL, 26, 0, 0),
  1003. GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
  1004. ENABLE_ACLK_MSCL, 25, 0, 0),
  1005. GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
  1006. ENABLE_ACLK_MSCL, 24, 0, 0),
  1007. GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
  1008. "usermux_aclk_mscl_532",
  1009. ENABLE_ACLK_MSCL, 23, 0, 0),
  1010. GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
  1011. ENABLE_ACLK_MSCL, 22, 0, 0),
  1012. GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
  1013. ENABLE_ACLK_MSCL, 21, 0, 0),
  1014. GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
  1015. ENABLE_ACLK_MSCL, 20, 0, 0),
  1016. GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
  1017. ENABLE_ACLK_MSCL, 19, 0, 0),
  1018. GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
  1019. ENABLE_ACLK_MSCL, 18, 0, 0),
  1020. GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
  1021. ENABLE_ACLK_MSCL, 17, 0, 0),
  1022. GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
  1023. ENABLE_ACLK_MSCL, 16, 0, 0),
  1024. GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
  1025. "usermux_aclk_mscl_532",
  1026. ENABLE_ACLK_MSCL, 15, 0, 0),
  1027. GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
  1028. "usermux_aclk_mscl_532",
  1029. ENABLE_ACLK_MSCL, 14, 0, 0),
  1030. GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
  1031. ENABLE_PCLK_MSCL, 31, 0, 0),
  1032. GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
  1033. ENABLE_PCLK_MSCL, 30, 0, 0),
  1034. GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
  1035. ENABLE_PCLK_MSCL, 29, 0, 0),
  1036. GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
  1037. ENABLE_PCLK_MSCL, 28, 0, 0),
  1038. GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
  1039. ENABLE_PCLK_MSCL, 27, 0, 0),
  1040. GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
  1041. ENABLE_PCLK_MSCL, 26, 0, 0),
  1042. GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
  1043. ENABLE_PCLK_MSCL, 25, 0, 0),
  1044. GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
  1045. ENABLE_PCLK_MSCL, 24, 0, 0),
  1046. GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
  1047. ENABLE_PCLK_MSCL, 23, 0, 0),
  1048. GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
  1049. ENABLE_PCLK_MSCL, 22, 0, 0),
  1050. GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
  1051. ENABLE_PCLK_MSCL, 21, 0, 0),
  1052. GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
  1053. ENABLE_PCLK_MSCL, 20, 0, 0),
  1054. };
  1055. static const struct samsung_cmu_info mscl_cmu_info __initconst = {
  1056. .mux_clks = mscl_mux_clks,
  1057. .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
  1058. .div_clks = mscl_div_clks,
  1059. .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
  1060. .gate_clks = mscl_gate_clks,
  1061. .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
  1062. .nr_clk_ids = MSCL_NR_CLK,
  1063. .clk_regs = mscl_clk_regs,
  1064. .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
  1065. };
  1066. static void __init exynos7_clk_mscl_init(struct device_node *np)
  1067. {
  1068. samsung_cmu_register_one(np, &mscl_cmu_info);
  1069. }
  1070. CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
  1071. exynos7_clk_mscl_init);
  1072. /* Register Offset definitions for CMU_AUD (0x114C0000) */
  1073. #define MUX_SEL_AUD 0x0200
  1074. #define DIV_AUD0 0x0600
  1075. #define DIV_AUD1 0x0604
  1076. #define ENABLE_ACLK_AUD 0x0800
  1077. #define ENABLE_PCLK_AUD 0x0900
  1078. #define ENABLE_SCLK_AUD 0x0A00
  1079. /*
  1080. * List of parent clocks for Muxes in CMU_AUD
  1081. */
  1082. PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
  1083. PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
  1084. static const unsigned long aud_clk_regs[] __initconst = {
  1085. MUX_SEL_AUD,
  1086. DIV_AUD0,
  1087. DIV_AUD1,
  1088. ENABLE_ACLK_AUD,
  1089. ENABLE_PCLK_AUD,
  1090. ENABLE_SCLK_AUD,
  1091. };
  1092. static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
  1093. MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
  1094. MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
  1095. MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
  1096. };
  1097. static const struct samsung_div_clock aud_div_clks[] __initconst = {
  1098. DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
  1099. DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
  1100. DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
  1101. DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
  1102. DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
  1103. DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
  1104. DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
  1105. DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
  1106. };
  1107. static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
  1108. GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
  1109. ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
  1110. GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
  1111. ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
  1112. GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
  1113. GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
  1114. ENABLE_SCLK_AUD, 30, 0, 0),
  1115. GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
  1116. GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
  1117. GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
  1118. GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
  1119. GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
  1120. GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
  1121. GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
  1122. ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
  1123. GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
  1124. ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
  1125. GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
  1126. GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
  1127. GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
  1128. GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
  1129. ENABLE_ACLK_AUD, 28, 0, 0),
  1130. GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
  1131. };
  1132. static const struct samsung_cmu_info aud_cmu_info __initconst = {
  1133. .mux_clks = aud_mux_clks,
  1134. .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
  1135. .div_clks = aud_div_clks,
  1136. .nr_div_clks = ARRAY_SIZE(aud_div_clks),
  1137. .gate_clks = aud_gate_clks,
  1138. .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
  1139. .nr_clk_ids = AUD_NR_CLK,
  1140. .clk_regs = aud_clk_regs,
  1141. .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
  1142. };
  1143. static void __init exynos7_clk_aud_init(struct device_node *np)
  1144. {
  1145. samsung_cmu_register_one(np, &aud_cmu_info);
  1146. }
  1147. CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
  1148. exynos7_clk_aud_init);