clk-exynos5420.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Authors: Thomas Abraham <thomas.ab@samsung.com>
  5. * Chander Kashyap <k.chander@samsung.com>
  6. *
  7. * Common Clock Framework support for Exynos5420 SoC.
  8. */
  9. #include <dt-bindings/clock/exynos5420.h>
  10. #include <linux/slab.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/clk.h>
  15. #include "clk.h"
  16. #include "clk-cpu.h"
  17. #include "clk-exynos5-subcmu.h"
  18. #define APLL_LOCK 0x0
  19. #define APLL_CON0 0x100
  20. #define SRC_CPU 0x200
  21. #define DIV_CPU0 0x500
  22. #define DIV_CPU1 0x504
  23. #define GATE_BUS_CPU 0x700
  24. #define GATE_SCLK_CPU 0x800
  25. #define CLKOUT_CMU_CPU 0xa00
  26. #define SRC_MASK_CPERI 0x4300
  27. #define GATE_IP_G2D 0x8800
  28. #define CPLL_LOCK 0x10020
  29. #define DPLL_LOCK 0x10030
  30. #define EPLL_LOCK 0x10040
  31. #define RPLL_LOCK 0x10050
  32. #define IPLL_LOCK 0x10060
  33. #define SPLL_LOCK 0x10070
  34. #define VPLL_LOCK 0x10080
  35. #define MPLL_LOCK 0x10090
  36. #define CPLL_CON0 0x10120
  37. #define DPLL_CON0 0x10128
  38. #define EPLL_CON0 0x10130
  39. #define EPLL_CON1 0x10134
  40. #define EPLL_CON2 0x10138
  41. #define RPLL_CON0 0x10140
  42. #define RPLL_CON1 0x10144
  43. #define RPLL_CON2 0x10148
  44. #define IPLL_CON0 0x10150
  45. #define SPLL_CON0 0x10160
  46. #define VPLL_CON0 0x10170
  47. #define MPLL_CON0 0x10180
  48. #define SRC_TOP0 0x10200
  49. #define SRC_TOP1 0x10204
  50. #define SRC_TOP2 0x10208
  51. #define SRC_TOP3 0x1020c
  52. #define SRC_TOP4 0x10210
  53. #define SRC_TOP5 0x10214
  54. #define SRC_TOP6 0x10218
  55. #define SRC_TOP7 0x1021c
  56. #define SRC_TOP8 0x10220 /* 5800 specific */
  57. #define SRC_TOP9 0x10224 /* 5800 specific */
  58. #define SRC_DISP10 0x1022c
  59. #define SRC_MAU 0x10240
  60. #define SRC_FSYS 0x10244
  61. #define SRC_PERIC0 0x10250
  62. #define SRC_PERIC1 0x10254
  63. #define SRC_ISP 0x10270
  64. #define SRC_CAM 0x10274 /* 5800 specific */
  65. #define SRC_TOP10 0x10280
  66. #define SRC_TOP11 0x10284
  67. #define SRC_TOP12 0x10288
  68. #define SRC_TOP13 0x1028c /* 5800 specific */
  69. #define SRC_MASK_TOP0 0x10300
  70. #define SRC_MASK_TOP1 0x10304
  71. #define SRC_MASK_TOP2 0x10308
  72. #define SRC_MASK_TOP7 0x1031c
  73. #define SRC_MASK_DISP10 0x1032c
  74. #define SRC_MASK_MAU 0x10334
  75. #define SRC_MASK_FSYS 0x10340
  76. #define SRC_MASK_PERIC0 0x10350
  77. #define SRC_MASK_PERIC1 0x10354
  78. #define SRC_MASK_ISP 0x10370
  79. #define DIV_TOP0 0x10500
  80. #define DIV_TOP1 0x10504
  81. #define DIV_TOP2 0x10508
  82. #define DIV_TOP8 0x10520 /* 5800 specific */
  83. #define DIV_TOP9 0x10524 /* 5800 specific */
  84. #define DIV_DISP10 0x1052c
  85. #define DIV_MAU 0x10544
  86. #define DIV_FSYS0 0x10548
  87. #define DIV_FSYS1 0x1054c
  88. #define DIV_FSYS2 0x10550
  89. #define DIV_PERIC0 0x10558
  90. #define DIV_PERIC1 0x1055c
  91. #define DIV_PERIC2 0x10560
  92. #define DIV_PERIC3 0x10564
  93. #define DIV_PERIC4 0x10568
  94. #define DIV_CAM 0x10574 /* 5800 specific */
  95. #define SCLK_DIV_ISP0 0x10580
  96. #define SCLK_DIV_ISP1 0x10584
  97. #define DIV2_RATIO0 0x10590
  98. #define DIV4_RATIO 0x105a0
  99. #define GATE_BUS_TOP 0x10700
  100. #define GATE_BUS_DISP1 0x10728
  101. #define GATE_BUS_GEN 0x1073c
  102. #define GATE_BUS_FSYS0 0x10740
  103. #define GATE_BUS_FSYS2 0x10748
  104. #define GATE_BUS_PERIC 0x10750
  105. #define GATE_BUS_PERIC1 0x10754
  106. #define GATE_BUS_PERIS0 0x10760
  107. #define GATE_BUS_PERIS1 0x10764
  108. #define GATE_BUS_NOC 0x10770
  109. #define GATE_TOP_SCLK_ISP 0x10870
  110. #define GATE_IP_GSCL0 0x10910
  111. #define GATE_IP_GSCL1 0x10920
  112. #define GATE_IP_CAM 0x10924 /* 5800 specific */
  113. #define GATE_IP_MFC 0x1092c
  114. #define GATE_IP_DISP1 0x10928
  115. #define GATE_IP_G3D 0x10930
  116. #define GATE_IP_GEN 0x10934
  117. #define GATE_IP_FSYS 0x10944
  118. #define GATE_IP_PERIC 0x10950
  119. #define GATE_IP_PERIS 0x10960
  120. #define GATE_IP_MSCL 0x10970
  121. #define GATE_TOP_SCLK_GSCL 0x10820
  122. #define GATE_TOP_SCLK_DISP1 0x10828
  123. #define GATE_TOP_SCLK_MAU 0x1083c
  124. #define GATE_TOP_SCLK_FSYS 0x10840
  125. #define GATE_TOP_SCLK_PERIC 0x10850
  126. #define TOP_SPARE2 0x10b08
  127. #define BPLL_LOCK 0x20010
  128. #define BPLL_CON0 0x20110
  129. #define SRC_CDREX 0x20200
  130. #define DIV_CDREX0 0x20500
  131. #define DIV_CDREX1 0x20504
  132. #define GATE_BUS_CDREX0 0x20700
  133. #define GATE_BUS_CDREX1 0x20704
  134. #define KPLL_LOCK 0x28000
  135. #define KPLL_CON0 0x28100
  136. #define SRC_KFC 0x28200
  137. #define DIV_KFC0 0x28500
  138. /* Exynos5x SoC type */
  139. enum exynos5x_soc {
  140. EXYNOS5420,
  141. EXYNOS5800,
  142. };
  143. /* list of PLLs */
  144. enum exynos5x_plls {
  145. apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
  146. bpll, kpll,
  147. nr_plls /* number of PLLs */
  148. };
  149. static void __iomem *reg_base;
  150. static enum exynos5x_soc exynos5x_soc;
  151. /*
  152. * list of controller registers to be saved and restored during a
  153. * suspend/resume cycle.
  154. */
  155. static const unsigned long exynos5x_clk_regs[] __initconst = {
  156. SRC_CPU,
  157. DIV_CPU0,
  158. DIV_CPU1,
  159. GATE_BUS_CPU,
  160. GATE_SCLK_CPU,
  161. CLKOUT_CMU_CPU,
  162. APLL_CON0,
  163. KPLL_CON0,
  164. CPLL_CON0,
  165. DPLL_CON0,
  166. EPLL_CON0,
  167. EPLL_CON1,
  168. EPLL_CON2,
  169. RPLL_CON0,
  170. RPLL_CON1,
  171. RPLL_CON2,
  172. IPLL_CON0,
  173. SPLL_CON0,
  174. VPLL_CON0,
  175. MPLL_CON0,
  176. SRC_TOP0,
  177. SRC_TOP1,
  178. SRC_TOP2,
  179. SRC_TOP3,
  180. SRC_TOP4,
  181. SRC_TOP5,
  182. SRC_TOP6,
  183. SRC_TOP7,
  184. SRC_DISP10,
  185. SRC_MAU,
  186. SRC_FSYS,
  187. SRC_PERIC0,
  188. SRC_PERIC1,
  189. SRC_TOP10,
  190. SRC_TOP11,
  191. SRC_TOP12,
  192. SRC_MASK_TOP2,
  193. SRC_MASK_TOP7,
  194. SRC_MASK_DISP10,
  195. SRC_MASK_FSYS,
  196. SRC_MASK_PERIC0,
  197. SRC_MASK_PERIC1,
  198. SRC_MASK_TOP0,
  199. SRC_MASK_TOP1,
  200. SRC_MASK_MAU,
  201. SRC_MASK_ISP,
  202. SRC_ISP,
  203. DIV_TOP0,
  204. DIV_TOP1,
  205. DIV_TOP2,
  206. DIV_DISP10,
  207. DIV_MAU,
  208. DIV_FSYS0,
  209. DIV_FSYS1,
  210. DIV_FSYS2,
  211. DIV_PERIC0,
  212. DIV_PERIC1,
  213. DIV_PERIC2,
  214. DIV_PERIC3,
  215. DIV_PERIC4,
  216. SCLK_DIV_ISP0,
  217. SCLK_DIV_ISP1,
  218. DIV2_RATIO0,
  219. DIV4_RATIO,
  220. GATE_BUS_DISP1,
  221. GATE_BUS_TOP,
  222. GATE_BUS_GEN,
  223. GATE_BUS_FSYS0,
  224. GATE_BUS_FSYS2,
  225. GATE_BUS_PERIC,
  226. GATE_BUS_PERIC1,
  227. GATE_BUS_PERIS0,
  228. GATE_BUS_PERIS1,
  229. GATE_BUS_NOC,
  230. GATE_TOP_SCLK_ISP,
  231. GATE_IP_GSCL0,
  232. GATE_IP_GSCL1,
  233. GATE_IP_MFC,
  234. GATE_IP_DISP1,
  235. GATE_IP_G3D,
  236. GATE_IP_GEN,
  237. GATE_IP_FSYS,
  238. GATE_IP_PERIC,
  239. GATE_IP_PERIS,
  240. GATE_IP_MSCL,
  241. GATE_TOP_SCLK_GSCL,
  242. GATE_TOP_SCLK_DISP1,
  243. GATE_TOP_SCLK_MAU,
  244. GATE_TOP_SCLK_FSYS,
  245. GATE_TOP_SCLK_PERIC,
  246. TOP_SPARE2,
  247. SRC_CDREX,
  248. DIV_CDREX0,
  249. DIV_CDREX1,
  250. SRC_KFC,
  251. DIV_KFC0,
  252. GATE_BUS_CDREX0,
  253. GATE_BUS_CDREX1,
  254. };
  255. static const unsigned long exynos5800_clk_regs[] __initconst = {
  256. SRC_TOP8,
  257. SRC_TOP9,
  258. SRC_CAM,
  259. SRC_TOP1,
  260. DIV_TOP8,
  261. DIV_TOP9,
  262. DIV_CAM,
  263. GATE_IP_CAM,
  264. };
  265. static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
  266. { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
  267. { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
  268. { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
  269. { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
  270. { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
  271. { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
  272. { .offset = SRC_MASK_MAU, .value = 0x10000000, },
  273. { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
  274. { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
  275. { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
  276. { .offset = SRC_MASK_ISP, .value = 0x11111000, },
  277. { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
  278. { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
  279. { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
  280. { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
  281. };
  282. /* list of all parent clocks */
  283. PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
  284. "mout_sclk_mpll", "mout_sclk_spll"};
  285. PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
  286. PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
  287. PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
  288. PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
  289. PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
  290. PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
  291. PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
  292. PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
  293. PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
  294. PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
  295. PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
  296. PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
  297. PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
  298. PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
  299. "mout_sclk_mpll"};
  300. PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
  301. "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
  302. "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
  303. PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
  304. PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
  305. PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
  306. PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
  307. PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
  308. PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
  309. PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
  310. PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
  311. PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
  312. PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
  313. PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
  314. PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
  315. PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
  316. PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
  317. PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
  318. PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
  319. PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
  320. PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
  321. PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
  322. PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
  323. PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
  324. "mout_sclk_spll"};
  325. PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
  326. PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
  327. PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
  328. PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
  329. PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
  330. PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
  331. PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
  332. PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
  333. PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
  334. PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
  335. PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
  336. PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
  337. PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
  338. PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
  339. PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
  340. PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
  341. PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
  342. PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
  343. PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
  344. PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
  345. PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
  346. PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
  347. PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
  348. PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
  349. PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
  350. PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
  351. PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
  352. PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
  353. PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
  354. PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
  355. PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
  356. "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
  357. "mout_sclk_epll", "mout_sclk_rpll"};
  358. PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
  359. "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
  360. "mout_sclk_epll", "mout_sclk_rpll"};
  361. PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
  362. "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
  363. "mout_sclk_epll", "mout_sclk_rpll"};
  364. PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
  365. "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
  366. "mout_sclk_epll", "mout_sclk_rpll"};
  367. PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
  368. PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
  369. "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
  370. "mout_sclk_epll", "mout_sclk_rpll"};
  371. PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
  372. "mout_sclk_mpll", "mout_sclk_spll"};
  373. PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
  374. /* List of parents specific to exynos5800 */
  375. PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
  376. PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
  377. "mout_sclk_mpll", "ff_dout_spll2" };
  378. PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
  379. "mout_sclk_mpll", "ff_dout_spll2",
  380. "mout_epll2", "mout_sclk_ipll" };
  381. PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
  382. "mout_sclk_mpll", "ff_dout_spll2",
  383. "mout_epll2" };
  384. PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
  385. "mout_sclk_mpll", "mout_sclk_spll" };
  386. PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
  387. "mout_sclk_mpll", "ff_dout_spll2" };
  388. PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
  389. "mout_sclk_mpll", "mout_sclk_spll",
  390. "mout_epll2", "mout_sclk_ipll" };
  391. PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll",
  392. "mout_sclk_mpll", "ff_dout_spll2",
  393. "mout_sclk_spll", "mout_sclk_epll"};
  394. PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
  395. "mout_sclk_mpll",
  396. "ff_dout_spll2" };
  397. PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
  398. PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
  399. PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
  400. PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
  401. PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
  402. PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
  403. PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
  404. PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
  405. PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
  406. PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
  407. "mout_sclk_mpll", "ff_dout_spll2",
  408. "mout_sclk_spll", "mout_sclk_epll"};
  409. /* fixed rate clocks generated outside the soc */
  410. static struct samsung_fixed_rate_clock
  411. exynos5x_fixed_rate_ext_clks[] __initdata = {
  412. FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
  413. };
  414. /* fixed rate clocks generated inside the soc */
  415. static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
  416. FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
  417. FRATE(0, "sclk_pwi", NULL, 0, 24000000),
  418. FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
  419. FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
  420. FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
  421. };
  422. static const struct samsung_fixed_factor_clock
  423. exynos5x_fixed_factor_clks[] __initconst = {
  424. FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
  425. FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
  426. };
  427. static const struct samsung_fixed_factor_clock
  428. exynos5800_fixed_factor_clks[] __initconst = {
  429. FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
  430. FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
  431. };
  432. static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
  433. MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
  434. MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
  435. MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
  436. MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
  437. MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
  438. MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
  439. MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
  440. MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
  441. MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
  442. MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
  443. MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
  444. MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
  445. MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
  446. MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
  447. MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
  448. MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
  449. mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
  450. MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
  451. mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
  452. MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
  453. SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
  454. MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
  455. MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
  456. MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
  457. MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
  458. MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
  459. MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
  460. MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
  461. SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
  462. MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
  463. SRC_TOP9, 16, 1),
  464. MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
  465. SRC_TOP9, 20, 1),
  466. MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
  467. SRC_TOP9, 24, 1),
  468. MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
  469. SRC_TOP9, 28, 1),
  470. MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
  471. MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
  472. SRC_TOP13, 20, 1),
  473. MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
  474. SRC_TOP13, 24, 1),
  475. MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
  476. SRC_TOP13, 28, 1),
  477. MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
  478. };
  479. static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
  480. DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
  481. "mout_aclk400_wcore", DIV_TOP0, 16, 3),
  482. DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
  483. DIV_TOP8, 16, 3),
  484. DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
  485. DIV_TOP8, 20, 3),
  486. DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
  487. DIV_TOP8, 24, 3),
  488. DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
  489. DIV_TOP8, 28, 3),
  490. DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
  491. DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
  492. };
  493. static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
  494. GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
  495. GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
  496. GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
  497. GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
  498. };
  499. static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
  500. MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
  501. MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
  502. TOP_SPARE2, 4, 1),
  503. MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
  504. MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
  505. MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
  506. MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
  507. MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
  508. MUX(0, "mout_aclk333_432_isp", mout_group4_p,
  509. SRC_TOP1, 4, 2),
  510. MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
  511. MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
  512. MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
  513. MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
  514. MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
  515. MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
  516. MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
  517. MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
  518. MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
  519. MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
  520. mout_group5_5800_p, SRC_TOP7, 16, 2),
  521. MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
  522. CLK_SET_RATE_PARENT, 0),
  523. MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
  524. };
  525. static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
  526. DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
  527. "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
  528. };
  529. static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
  530. GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
  531. /* Maudio Block */
  532. GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
  533. SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
  534. GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
  535. GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
  536. GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
  537. GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
  538. };
  539. static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
  540. MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
  541. SRC_TOP7, 4, 1),
  542. MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p,
  543. SRC_TOP7, 8, 2),
  544. MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p,
  545. SRC_TOP7, 12, 2),
  546. MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
  547. CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
  548. MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
  549. MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
  550. CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
  551. MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
  552. MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
  553. MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
  554. MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
  555. MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
  556. MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
  557. MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
  558. MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
  559. CLK_SET_RATE_PARENT, 0),
  560. MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
  561. SRC_TOP3, 0, 1),
  562. MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
  563. SRC_TOP3, 4, 1),
  564. MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
  565. mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
  566. MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
  567. SRC_TOP3, 12, 1),
  568. MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
  569. SRC_TOP3, 16, 1),
  570. MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
  571. SRC_TOP3, 20, 1),
  572. MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
  573. SRC_TOP3, 24, 1),
  574. MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
  575. SRC_TOP3, 28, 1),
  576. MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
  577. SRC_TOP4, 0, 1),
  578. MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
  579. SRC_TOP4, 4, 1),
  580. MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
  581. SRC_TOP4, 8, 1),
  582. MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
  583. SRC_TOP4, 12, 1),
  584. MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
  585. SRC_TOP4, 16, 1),
  586. MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
  587. MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
  588. MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
  589. SRC_TOP4, 28, 1),
  590. MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
  591. mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
  592. MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
  593. SRC_TOP5, 4, 1),
  594. MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
  595. SRC_TOP5, 8, 1),
  596. MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
  597. SRC_TOP5, 12, 1),
  598. MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
  599. SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
  600. MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
  601. SRC_TOP5, 20, 1),
  602. MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
  603. mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
  604. MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
  605. mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
  606. MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
  607. MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
  608. CLK_SET_RATE_PARENT, 0),
  609. MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
  610. MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
  611. MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
  612. MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
  613. CLK_SET_RATE_PARENT, 0),
  614. MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
  615. MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
  616. MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
  617. SRC_TOP10, 0, 1),
  618. MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
  619. SRC_TOP10, 4, 1),
  620. MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
  621. SRC_TOP10, 8, 1),
  622. MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
  623. SRC_TOP10, 12, 1),
  624. MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
  625. SRC_TOP10, 16, 1),
  626. MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
  627. SRC_TOP10, 20, 1),
  628. MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
  629. SRC_TOP10, 24, 1),
  630. MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
  631. SRC_TOP10, 28, 1),
  632. MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
  633. SRC_TOP11, 0, 1),
  634. MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
  635. SRC_TOP11, 4, 1),
  636. MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
  637. MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
  638. SRC_TOP11, 12, 1),
  639. MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
  640. MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
  641. MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
  642. SRC_TOP11, 28, 1),
  643. MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
  644. mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
  645. MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
  646. SRC_TOP12, 8, 1),
  647. MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
  648. SRC_TOP12, 12, 1),
  649. MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
  650. SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
  651. MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
  652. SRC_TOP12, 20, 1),
  653. MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
  654. mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
  655. MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
  656. mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
  657. /* DISP1 Block */
  658. MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
  659. MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
  660. MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
  661. MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
  662. MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
  663. MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
  664. /* CDREX block */
  665. MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
  666. SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
  667. MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
  668. CLK_SET_RATE_PARENT, 0),
  669. /* MAU Block */
  670. MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
  671. /* FSYS Block */
  672. MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
  673. MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
  674. MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
  675. MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
  676. MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
  677. MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
  678. MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
  679. /* PERIC Block */
  680. MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
  681. MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
  682. MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
  683. MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
  684. MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
  685. MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
  686. MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
  687. MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
  688. MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
  689. MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
  690. MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
  691. MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
  692. /* ISP Block */
  693. MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
  694. MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
  695. MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
  696. MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
  697. MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
  698. };
  699. static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
  700. DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
  701. DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
  702. DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
  703. DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
  704. DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
  705. DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
  706. DIV_TOP0, 0, 3),
  707. DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
  708. DIV_TOP0, 4, 3),
  709. DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
  710. DIV_TOP0, 8, 3),
  711. DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
  712. DIV_TOP0, 12, 3),
  713. DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
  714. DIV_TOP0, 20, 3),
  715. DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
  716. DIV_TOP0, 24, 3),
  717. DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
  718. DIV_TOP0, 28, 3),
  719. DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
  720. "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
  721. DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
  722. "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
  723. DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
  724. DIV_TOP1, 8, 6),
  725. DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
  726. "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
  727. DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
  728. DIV_TOP1, 20, 3),
  729. DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
  730. DIV_TOP1, 24, 3),
  731. DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
  732. DIV_TOP1, 28, 3),
  733. DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
  734. DIV_TOP2, 8, 3),
  735. DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
  736. DIV_TOP2, 12, 3),
  737. DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
  738. 16, 3, CLK_SET_RATE_PARENT, 0),
  739. DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
  740. DIV_TOP2, 20, 3),
  741. DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
  742. "mout_aclk300_disp1", DIV_TOP2, 24, 3),
  743. DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
  744. DIV_TOP2, 28, 3),
  745. /* DISP1 Block */
  746. DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
  747. DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
  748. DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
  749. DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
  750. DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
  751. "mout_aclk400_disp1", DIV_TOP2, 4, 3),
  752. /* CDREX Block */
  753. /*
  754. * The three clocks below are controlled using the same register and
  755. * bits. They are put into one because there is a need of
  756. * synchronization between the BUS and DREXs (two external memory
  757. * interfaces).
  758. * They are put here to show this HW assumption and for clock
  759. * information summary completeness.
  760. */
  761. DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
  762. DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
  763. DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
  764. DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
  765. DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
  766. DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
  767. DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
  768. DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
  769. DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
  770. DIV_CDREX0, 16, 3),
  771. DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
  772. DIV_CDREX0, 8, 3),
  773. DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
  774. DIV_CDREX0, 3, 5),
  775. DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
  776. DIV_CDREX1, 8, 3),
  777. /* Audio Block */
  778. DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
  779. DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
  780. /* USB3.0 */
  781. DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
  782. DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
  783. DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
  784. DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
  785. /* MMC */
  786. DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
  787. DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
  788. DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
  789. DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
  790. DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
  791. /* UART and PWM */
  792. DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
  793. DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
  794. DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
  795. DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
  796. DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
  797. /* SPI */
  798. DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
  799. DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
  800. DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
  801. /* PCM */
  802. DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
  803. DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
  804. /* Audio - I2S */
  805. DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
  806. DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
  807. DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
  808. DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
  809. DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
  810. /* SPI Pre-Ratio */
  811. DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
  812. DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
  813. DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
  814. /* GSCL Block */
  815. DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
  816. /* PSGEN */
  817. DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
  818. DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
  819. /* ISP Block */
  820. DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
  821. DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
  822. DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
  823. DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
  824. DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
  825. DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
  826. DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
  827. DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
  828. CLK_SET_RATE_PARENT, 0),
  829. DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
  830. CLK_SET_RATE_PARENT, 0),
  831. };
  832. static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
  833. /* G2D */
  834. GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
  835. GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
  836. GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
  837. GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
  838. GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
  839. GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
  840. GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
  841. GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
  842. GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
  843. GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
  844. GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
  845. GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
  846. GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
  847. GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
  848. GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
  849. GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
  850. GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
  851. GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
  852. GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
  853. GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
  854. GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
  855. GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
  856. GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
  857. GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
  858. GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
  859. GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
  860. GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
  861. GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
  862. GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
  863. GATE(0, "aclk166", "mout_user_aclk166",
  864. GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
  865. GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
  866. GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
  867. GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
  868. GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
  869. GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
  870. GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
  871. GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
  872. GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
  873. GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
  874. GATE_BUS_TOP, 28, 0, 0),
  875. GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
  876. GATE_BUS_TOP, 29, 0, 0),
  877. GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
  878. SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
  879. /* sclk */
  880. GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
  881. GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
  882. GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
  883. GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
  884. GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
  885. GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
  886. GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
  887. GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
  888. GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
  889. GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
  890. GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
  891. GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
  892. GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
  893. GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
  894. GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
  895. GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
  896. GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
  897. GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
  898. GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
  899. GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
  900. GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
  901. GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
  902. GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
  903. GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
  904. GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
  905. GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
  906. GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
  907. GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
  908. GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
  909. GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
  910. GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
  911. GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
  912. GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
  913. GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
  914. GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
  915. GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
  916. GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
  917. GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
  918. GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
  919. GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
  920. /* Display */
  921. GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
  922. GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
  923. GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
  924. GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
  925. GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
  926. GATE_TOP_SCLK_DISP1, 9, 0, 0),
  927. GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
  928. GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
  929. GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
  930. GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
  931. /* FSYS Block */
  932. GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
  933. GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
  934. GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
  935. GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
  936. GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
  937. GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
  938. GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
  939. GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
  940. GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
  941. GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
  942. GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
  943. GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
  944. GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
  945. GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
  946. SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
  947. /* PERIC Block */
  948. GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
  949. GATE_IP_PERIC, 0, 0, 0),
  950. GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
  951. GATE_IP_PERIC, 1, 0, 0),
  952. GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
  953. GATE_IP_PERIC, 2, 0, 0),
  954. GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
  955. GATE_IP_PERIC, 3, 0, 0),
  956. GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
  957. GATE_IP_PERIC, 6, 0, 0),
  958. GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
  959. GATE_IP_PERIC, 7, 0, 0),
  960. GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
  961. GATE_IP_PERIC, 8, 0, 0),
  962. GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
  963. GATE_IP_PERIC, 9, 0, 0),
  964. GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
  965. GATE_IP_PERIC, 10, 0, 0),
  966. GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
  967. GATE_IP_PERIC, 11, 0, 0),
  968. GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
  969. GATE_IP_PERIC, 12, 0, 0),
  970. GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
  971. GATE_IP_PERIC, 13, 0, 0),
  972. GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
  973. GATE_IP_PERIC, 14, 0, 0),
  974. GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
  975. GATE_IP_PERIC, 15, 0, 0),
  976. GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
  977. GATE_IP_PERIC, 16, 0, 0),
  978. GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
  979. GATE_IP_PERIC, 17, 0, 0),
  980. GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
  981. GATE_IP_PERIC, 18, 0, 0),
  982. GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
  983. GATE_IP_PERIC, 20, 0, 0),
  984. GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
  985. GATE_IP_PERIC, 21, 0, 0),
  986. GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
  987. GATE_IP_PERIC, 22, 0, 0),
  988. GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
  989. GATE_IP_PERIC, 23, 0, 0),
  990. GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
  991. GATE_IP_PERIC, 24, 0, 0),
  992. GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
  993. GATE_IP_PERIC, 26, 0, 0),
  994. GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
  995. GATE_IP_PERIC, 28, 0, 0),
  996. GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
  997. GATE_IP_PERIC, 30, 0, 0),
  998. GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
  999. GATE_IP_PERIC, 31, 0, 0),
  1000. GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
  1001. GATE_BUS_PERIC, 22, 0, 0),
  1002. /* PERIS Block */
  1003. GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
  1004. GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
  1005. GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
  1006. GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
  1007. GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
  1008. GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
  1009. GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
  1010. GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
  1011. GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
  1012. GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
  1013. GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
  1014. GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
  1015. GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
  1016. GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
  1017. GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
  1018. GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
  1019. GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
  1020. GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
  1021. GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
  1022. GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
  1023. /* GEN Block */
  1024. GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
  1025. GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
  1026. GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
  1027. GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
  1028. GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
  1029. GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
  1030. GATE_IP_GEN, 6, 0, 0),
  1031. GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
  1032. GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
  1033. GATE_IP_GEN, 9, 0, 0),
  1034. /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
  1035. GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
  1036. GATE_BUS_GEN, 28, 0, 0),
  1037. GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
  1038. /* GSCL Block */
  1039. GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
  1040. GATE_TOP_SCLK_GSCL, 6, 0, 0),
  1041. GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
  1042. GATE_TOP_SCLK_GSCL, 7, 0, 0),
  1043. GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
  1044. GATE_IP_GSCL0, 4, 0, 0),
  1045. GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
  1046. GATE_IP_GSCL0, 5, 0, 0),
  1047. GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
  1048. GATE_IP_GSCL0, 6, 0, 0),
  1049. GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
  1050. GATE_IP_GSCL1, 2, 0, 0),
  1051. GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
  1052. GATE_IP_GSCL1, 3, 0, 0),
  1053. GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
  1054. GATE_IP_GSCL1, 4, 0, 0),
  1055. GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12,
  1056. CLK_IS_CRITICAL, 0),
  1057. GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
  1058. CLK_IS_CRITICAL, 0),
  1059. GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333",
  1060. GATE_IP_GSCL1, 16, 0, 0),
  1061. GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
  1062. GATE_IP_GSCL1, 17, 0, 0),
  1063. /* ISP */
  1064. GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
  1065. GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
  1066. GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
  1067. GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
  1068. GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
  1069. GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
  1070. GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
  1071. GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
  1072. GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
  1073. GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
  1074. GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
  1075. GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
  1076. GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
  1077. GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
  1078. /* CDREX */
  1079. GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
  1080. GATE_BUS_CDREX0, 0, 0, 0),
  1081. GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
  1082. GATE_BUS_CDREX0, 1, 0, 0),
  1083. GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
  1084. SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
  1085. GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
  1086. GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
  1087. GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
  1088. GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
  1089. GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
  1090. GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
  1091. GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
  1092. GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
  1093. GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
  1094. GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
  1095. GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
  1096. GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
  1097. GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
  1098. GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
  1099. GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
  1100. GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
  1101. };
  1102. static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
  1103. DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
  1104. };
  1105. static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
  1106. GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
  1107. GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
  1108. GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
  1109. GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
  1110. GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
  1111. GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
  1112. GATE_IP_DISP1, 7, 0, 0),
  1113. GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
  1114. GATE_IP_DISP1, 8, 0, 0),
  1115. GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
  1116. GATE_IP_DISP1, 9, 0, 0),
  1117. };
  1118. static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
  1119. { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
  1120. { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
  1121. { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
  1122. { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
  1123. { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
  1124. };
  1125. static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
  1126. DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
  1127. DIV2_RATIO0, 4, 2),
  1128. };
  1129. static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
  1130. GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
  1131. GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
  1132. GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
  1133. GATE_IP_GSCL1, 6, 0, 0),
  1134. GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
  1135. GATE_IP_GSCL1, 7, 0, 0),
  1136. };
  1137. static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
  1138. { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
  1139. { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
  1140. { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
  1141. { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
  1142. };
  1143. static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
  1144. GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
  1145. CLK_SET_RATE_PARENT, 0),
  1146. };
  1147. static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
  1148. { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
  1149. { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
  1150. };
  1151. static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
  1152. DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
  1153. };
  1154. static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
  1155. GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
  1156. GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
  1157. GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
  1158. };
  1159. static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
  1160. { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
  1161. { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
  1162. { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
  1163. };
  1164. static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
  1165. /* MSCL Block */
  1166. GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
  1167. GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
  1168. GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
  1169. GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
  1170. GATE_IP_MSCL, 8, 0, 0),
  1171. GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
  1172. GATE_IP_MSCL, 9, 0, 0),
  1173. GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
  1174. GATE_IP_MSCL, 10, 0, 0),
  1175. };
  1176. static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
  1177. DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
  1178. };
  1179. static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
  1180. { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
  1181. { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
  1182. { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
  1183. };
  1184. static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
  1185. GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
  1186. SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
  1187. GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
  1188. GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
  1189. GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
  1190. GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
  1191. };
  1192. static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
  1193. { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
  1194. };
  1195. static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
  1196. .div_clks = exynos5x_disp_div_clks,
  1197. .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
  1198. .gate_clks = exynos5x_disp_gate_clks,
  1199. .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
  1200. .suspend_regs = exynos5x_disp_suspend_regs,
  1201. .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
  1202. .pd_name = "DISP",
  1203. };
  1204. static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
  1205. .div_clks = exynos5x_gsc_div_clks,
  1206. .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
  1207. .gate_clks = exynos5x_gsc_gate_clks,
  1208. .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
  1209. .suspend_regs = exynos5x_gsc_suspend_regs,
  1210. .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
  1211. .pd_name = "GSC",
  1212. };
  1213. static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
  1214. .gate_clks = exynos5x_g3d_gate_clks,
  1215. .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
  1216. .suspend_regs = exynos5x_g3d_suspend_regs,
  1217. .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
  1218. .pd_name = "G3D",
  1219. };
  1220. static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
  1221. .div_clks = exynos5x_mfc_div_clks,
  1222. .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
  1223. .gate_clks = exynos5x_mfc_gate_clks,
  1224. .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
  1225. .suspend_regs = exynos5x_mfc_suspend_regs,
  1226. .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
  1227. .pd_name = "MFC",
  1228. };
  1229. static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
  1230. .div_clks = exynos5x_mscl_div_clks,
  1231. .nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks),
  1232. .gate_clks = exynos5x_mscl_gate_clks,
  1233. .nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks),
  1234. .suspend_regs = exynos5x_mscl_suspend_regs,
  1235. .nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
  1236. .pd_name = "MSC",
  1237. };
  1238. static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
  1239. .gate_clks = exynos5800_mau_gate_clks,
  1240. .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks),
  1241. .suspend_regs = exynos5800_mau_suspend_regs,
  1242. .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
  1243. .pd_name = "MAU",
  1244. };
  1245. static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
  1246. &exynos5x_disp_subcmu,
  1247. &exynos5x_gsc_subcmu,
  1248. &exynos5x_g3d_subcmu,
  1249. &exynos5x_mfc_subcmu,
  1250. &exynos5x_mscl_subcmu,
  1251. };
  1252. static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
  1253. &exynos5x_disp_subcmu,
  1254. &exynos5x_gsc_subcmu,
  1255. &exynos5x_g3d_subcmu,
  1256. &exynos5x_mfc_subcmu,
  1257. &exynos5x_mscl_subcmu,
  1258. &exynos5800_mau_subcmu,
  1259. };
  1260. static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
  1261. PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
  1262. PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
  1263. PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
  1264. PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
  1265. PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
  1266. PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
  1267. PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
  1268. PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
  1269. PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
  1270. PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
  1271. PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
  1272. PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1),
  1273. PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
  1274. PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
  1275. PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2),
  1276. PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
  1277. PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
  1278. PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3),
  1279. PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
  1280. };
  1281. static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
  1282. PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
  1283. PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
  1284. PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
  1285. PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
  1286. PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
  1287. PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
  1288. PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
  1289. PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
  1290. };
  1291. static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
  1292. PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
  1293. PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
  1294. PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
  1295. PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
  1296. PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
  1297. PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
  1298. PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
  1299. PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
  1300. PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
  1301. PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923),
  1302. PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762),
  1303. PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719),
  1304. PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
  1305. PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762),
  1306. PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
  1307. };
  1308. static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
  1309. PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
  1310. PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
  1311. PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2),
  1312. PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
  1313. PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
  1314. PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
  1315. PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
  1316. PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
  1317. };
  1318. static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
  1319. [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
  1320. APLL_CON0, NULL),
  1321. [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
  1322. CPLL_CON0, NULL),
  1323. [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
  1324. DPLL_CON0, NULL),
  1325. [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
  1326. EPLL_CON0, NULL),
  1327. [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
  1328. RPLL_CON0, NULL),
  1329. [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
  1330. IPLL_CON0, NULL),
  1331. [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
  1332. SPLL_CON0, NULL),
  1333. [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
  1334. VPLL_CON0, NULL),
  1335. [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
  1336. MPLL_CON0, NULL),
  1337. [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
  1338. BPLL_CON0, NULL),
  1339. [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
  1340. KPLL_CON0, NULL),
  1341. };
  1342. #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
  1343. ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
  1344. ((cpud) << 4)))
  1345. static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
  1346. { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
  1347. { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1348. { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1349. { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1350. { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1351. { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
  1352. { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
  1353. { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
  1354. { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
  1355. { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
  1356. { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
  1357. { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
  1358. { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
  1359. { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
  1360. { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
  1361. { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
  1362. { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
  1363. { 0 },
  1364. };
  1365. static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
  1366. { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
  1367. { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
  1368. { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
  1369. { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1370. { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1371. { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1372. { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
  1373. { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
  1374. { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
  1375. { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
  1376. { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
  1377. { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
  1378. { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
  1379. { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
  1380. { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
  1381. { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
  1382. { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
  1383. { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
  1384. { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
  1385. { 0 },
  1386. };
  1387. #define E5420_KFC_DIV(kpll, pclk, aclk) \
  1388. ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
  1389. static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
  1390. { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
  1391. { 1300000, E5420_KFC_DIV(3, 5, 2), },
  1392. { 1200000, E5420_KFC_DIV(3, 5, 2), },
  1393. { 1100000, E5420_KFC_DIV(3, 5, 2), },
  1394. { 1000000, E5420_KFC_DIV(3, 5, 2), },
  1395. { 900000, E5420_KFC_DIV(3, 5, 2), },
  1396. { 800000, E5420_KFC_DIV(3, 5, 2), },
  1397. { 700000, E5420_KFC_DIV(3, 4, 2), },
  1398. { 600000, E5420_KFC_DIV(3, 4, 2), },
  1399. { 500000, E5420_KFC_DIV(3, 4, 2), },
  1400. { 400000, E5420_KFC_DIV(3, 3, 2), },
  1401. { 300000, E5420_KFC_DIV(3, 3, 2), },
  1402. { 200000, E5420_KFC_DIV(3, 3, 2), },
  1403. { 0 },
  1404. };
  1405. static const struct of_device_id ext_clk_match[] __initconst = {
  1406. { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
  1407. { },
  1408. };
  1409. /* register exynos5420 clocks */
  1410. static void __init exynos5x_clk_init(struct device_node *np,
  1411. enum exynos5x_soc soc)
  1412. {
  1413. struct samsung_clk_provider *ctx;
  1414. struct clk_hw **hws;
  1415. if (np) {
  1416. reg_base = of_iomap(np, 0);
  1417. if (!reg_base)
  1418. panic("%s: failed to map registers\n", __func__);
  1419. } else {
  1420. panic("%s: unable to determine soc\n", __func__);
  1421. }
  1422. exynos5x_soc = soc;
  1423. ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
  1424. hws = ctx->clk_data.hws;
  1425. samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
  1426. ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
  1427. ext_clk_match);
  1428. if (_get_rate("fin_pll") == 24 * MHZ) {
  1429. exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
  1430. exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
  1431. exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
  1432. exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
  1433. }
  1434. if (soc == EXYNOS5420)
  1435. exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
  1436. else
  1437. exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
  1438. samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
  1439. reg_base);
  1440. samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
  1441. ARRAY_SIZE(exynos5x_fixed_rate_clks));
  1442. samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
  1443. ARRAY_SIZE(exynos5x_fixed_factor_clks));
  1444. samsung_clk_register_mux(ctx, exynos5x_mux_clks,
  1445. ARRAY_SIZE(exynos5x_mux_clks));
  1446. samsung_clk_register_div(ctx, exynos5x_div_clks,
  1447. ARRAY_SIZE(exynos5x_div_clks));
  1448. samsung_clk_register_gate(ctx, exynos5x_gate_clks,
  1449. ARRAY_SIZE(exynos5x_gate_clks));
  1450. if (soc == EXYNOS5420) {
  1451. samsung_clk_register_mux(ctx, exynos5420_mux_clks,
  1452. ARRAY_SIZE(exynos5420_mux_clks));
  1453. samsung_clk_register_div(ctx, exynos5420_div_clks,
  1454. ARRAY_SIZE(exynos5420_div_clks));
  1455. samsung_clk_register_gate(ctx, exynos5420_gate_clks,
  1456. ARRAY_SIZE(exynos5420_gate_clks));
  1457. } else {
  1458. samsung_clk_register_fixed_factor(
  1459. ctx, exynos5800_fixed_factor_clks,
  1460. ARRAY_SIZE(exynos5800_fixed_factor_clks));
  1461. samsung_clk_register_mux(ctx, exynos5800_mux_clks,
  1462. ARRAY_SIZE(exynos5800_mux_clks));
  1463. samsung_clk_register_div(ctx, exynos5800_div_clks,
  1464. ARRAY_SIZE(exynos5800_div_clks));
  1465. samsung_clk_register_gate(ctx, exynos5800_gate_clks,
  1466. ARRAY_SIZE(exynos5800_gate_clks));
  1467. }
  1468. if (soc == EXYNOS5420) {
  1469. exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
  1470. hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
  1471. exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
  1472. } else {
  1473. exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
  1474. hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
  1475. exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
  1476. }
  1477. exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
  1478. hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
  1479. exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
  1480. samsung_clk_extended_sleep_init(reg_base,
  1481. exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
  1482. exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
  1483. if (soc == EXYNOS5800) {
  1484. samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
  1485. ARRAY_SIZE(exynos5800_clk_regs));
  1486. exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
  1487. exynos5800_subcmus);
  1488. } else {
  1489. exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
  1490. exynos5x_subcmus);
  1491. }
  1492. /*
  1493. * Keep top part of G3D clock path enabled permanently to ensure
  1494. * that the internal busses get their clock regardless of the
  1495. * main G3D clock enablement status.
  1496. */
  1497. clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
  1498. /*
  1499. * Keep top BPLL mux enabled permanently to ensure that DRAM operates
  1500. * properly.
  1501. */
  1502. clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
  1503. samsung_clk_of_add_provider(np, ctx);
  1504. }
  1505. static void __init exynos5420_clk_init(struct device_node *np)
  1506. {
  1507. exynos5x_clk_init(np, EXYNOS5420);
  1508. }
  1509. CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
  1510. exynos5420_clk_init);
  1511. static void __init exynos5800_clk_init(struct device_node *np)
  1512. {
  1513. exynos5x_clk_init(np, EXYNOS5800);
  1514. }
  1515. CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
  1516. exynos5800_clk_init);