clk-exynos5410.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Author: Tarek Dakhran <t.dakhran@samsung.com>
  5. *
  6. * Common Clock Framework support for Exynos5410 SoC.
  7. */
  8. #include <dt-bindings/clock/exynos5410.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <linux/clk.h>
  13. #include "clk.h"
  14. #define APLL_LOCK 0x0
  15. #define APLL_CON0 0x100
  16. #define CPLL_LOCK 0x10020
  17. #define CPLL_CON0 0x10120
  18. #define EPLL_LOCK 0x10040
  19. #define EPLL_CON0 0x10130
  20. #define MPLL_LOCK 0x4000
  21. #define MPLL_CON0 0x4100
  22. #define BPLL_LOCK 0x20010
  23. #define BPLL_CON0 0x20110
  24. #define KPLL_LOCK 0x28000
  25. #define KPLL_CON0 0x28100
  26. #define SRC_CPU 0x200
  27. #define DIV_CPU0 0x500
  28. #define SRC_CPERI1 0x4204
  29. #define GATE_IP_G2D 0x8800
  30. #define DIV_TOP0 0x10510
  31. #define DIV_TOP1 0x10514
  32. #define DIV_FSYS0 0x10548
  33. #define DIV_FSYS1 0x1054c
  34. #define DIV_FSYS2 0x10550
  35. #define DIV_PERIC0 0x10558
  36. #define DIV_PERIC3 0x10564
  37. #define SRC_TOP0 0x10210
  38. #define SRC_TOP1 0x10214
  39. #define SRC_TOP2 0x10218
  40. #define SRC_FSYS 0x10244
  41. #define SRC_PERIC0 0x10250
  42. #define SRC_MASK_FSYS 0x10340
  43. #define SRC_MASK_PERIC0 0x10350
  44. #define GATE_BUS_FSYS0 0x10740
  45. #define GATE_TOP_SCLK_FSYS 0x10840
  46. #define GATE_TOP_SCLK_PERIC 0x10850
  47. #define GATE_IP_FSYS 0x10944
  48. #define GATE_IP_PERIC 0x10950
  49. #define GATE_IP_PERIS 0x10960
  50. #define SRC_CDREX 0x20200
  51. #define SRC_KFC 0x28200
  52. #define DIV_KFC0 0x28500
  53. /* list of PLLs */
  54. enum exynos5410_plls {
  55. apll, cpll, epll, mpll,
  56. bpll, kpll,
  57. nr_plls /* number of PLLs */
  58. };
  59. /* list of all parent clocks */
  60. PNAME(apll_p) = { "fin_pll", "fout_apll", };
  61. PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
  62. PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
  63. PNAME(epll_p) = { "fin_pll", "fout_epll" };
  64. PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
  65. PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
  66. PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
  67. PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
  68. PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
  69. PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
  70. PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
  71. PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
  72. PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
  73. "none", "none", "sclk_mpll_bpll",
  74. "none", "none", "sclk_cpll" };
  75. static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = {
  76. MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
  77. MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
  78. MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
  79. MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
  80. MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
  81. MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
  82. MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
  83. MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
  84. MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
  85. MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
  86. MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
  87. MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
  88. MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
  89. MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
  90. MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
  91. MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
  92. MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
  93. MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
  94. MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
  95. MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
  96. MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
  97. MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
  98. MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
  99. };
  100. static const struct samsung_div_clock exynos5410_div_clks[] __initconst = {
  101. DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
  102. DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
  103. DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
  104. DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
  105. DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
  106. DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
  107. DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
  108. DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
  109. DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
  110. DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
  111. DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
  112. DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
  113. DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
  114. DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
  115. DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
  116. DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
  117. DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
  118. DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
  119. DIV_F(0, "div_mmc_pre0", "div_mmc0",
  120. DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
  121. DIV_F(0, "div_mmc_pre1", "div_mmc1",
  122. DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
  123. DIV_F(0, "div_mmc_pre2", "div_mmc2",
  124. DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
  125. DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
  126. DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
  127. DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
  128. DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
  129. DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
  130. DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
  131. DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
  132. DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
  133. };
  134. static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
  135. GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
  136. GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
  137. GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
  138. GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
  139. GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
  140. GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
  141. SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
  142. GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
  143. SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
  144. GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
  145. SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
  146. GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
  147. GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
  148. GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
  149. GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
  150. GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
  151. GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
  152. GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
  153. GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
  154. GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
  155. GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
  156. GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
  157. GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
  158. GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
  159. GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
  160. GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
  161. GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
  162. GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
  163. GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
  164. GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
  165. GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
  166. GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
  167. GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
  168. GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
  169. GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
  170. GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
  171. GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
  172. GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
  173. GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
  174. GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
  175. GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
  176. SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
  177. GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
  178. SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
  179. GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
  180. SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
  181. GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
  182. SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
  183. GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
  184. GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
  185. GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
  186. };
  187. static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = {
  188. PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
  189. PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
  190. PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
  191. PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
  192. PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
  193. PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
  194. PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
  195. PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
  196. PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
  197. PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
  198. };
  199. static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
  200. [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
  201. APLL_CON0, NULL),
  202. [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
  203. CPLL_CON0, NULL),
  204. [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
  205. EPLL_CON0, NULL),
  206. [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
  207. MPLL_CON0, NULL),
  208. [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
  209. BPLL_CON0, NULL),
  210. [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
  211. KPLL_CON0, NULL),
  212. };
  213. static const struct samsung_cmu_info cmu __initconst = {
  214. .pll_clks = exynos5410_plls,
  215. .nr_pll_clks = ARRAY_SIZE(exynos5410_plls),
  216. .mux_clks = exynos5410_mux_clks,
  217. .nr_mux_clks = ARRAY_SIZE(exynos5410_mux_clks),
  218. .div_clks = exynos5410_div_clks,
  219. .nr_div_clks = ARRAY_SIZE(exynos5410_div_clks),
  220. .gate_clks = exynos5410_gate_clks,
  221. .nr_gate_clks = ARRAY_SIZE(exynos5410_gate_clks),
  222. .nr_clk_ids = CLK_NR_CLKS,
  223. };
  224. /* register exynos5410 clocks */
  225. static void __init exynos5410_clk_init(struct device_node *np)
  226. {
  227. struct clk *xxti = of_clk_get(np, 0);
  228. if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ)
  229. exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl;
  230. samsung_cmu_register_one(np, &cmu);
  231. pr_debug("Exynos5410: clock setup completed.\n");
  232. }
  233. CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);