clk-exynos5260.c 63 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  4. * Author: Rahul Sharma <rahul.sharma@samsung.com>
  5. *
  6. * Common Clock Framework support for Exynos5260 SoC.
  7. */
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include "clk-exynos5260.h"
  11. #include "clk.h"
  12. #include "clk-pll.h"
  13. #include <dt-bindings/clock/exynos5260-clk.h>
  14. /*
  15. * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  16. * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
  17. */
  18. static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = {
  19. PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
  20. PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
  21. PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
  22. PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
  23. PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
  24. PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
  25. PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
  26. PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
  27. PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
  28. PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
  29. PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
  30. PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1),
  31. PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
  32. PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
  33. PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
  34. PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2),
  35. PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),
  36. PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2),
  37. PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),
  38. PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
  39. PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2),
  40. PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
  41. PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2),
  42. PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3),
  43. PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3),
  44. PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
  45. PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3),
  46. };
  47. /*
  48. * Applicable for 2650 Type PLL for AUD_PLL.
  49. */
  50. static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = {
  51. PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0),
  52. PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0),
  53. PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0),
  54. PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),
  55. PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),
  56. PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0),
  57. PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0),
  58. PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0),
  59. PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),
  60. PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282),
  61. PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),
  62. PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),
  63. PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
  64. PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0),
  65. PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0),
  66. PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0),
  67. PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0),
  68. PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0),
  69. };
  70. /* CMU_AUD */
  71. static const unsigned long aud_clk_regs[] __initconst = {
  72. MUX_SEL_AUD,
  73. DIV_AUD0,
  74. DIV_AUD1,
  75. EN_ACLK_AUD,
  76. EN_PCLK_AUD,
  77. EN_SCLK_AUD,
  78. EN_IP_AUD,
  79. };
  80. PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
  81. PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
  82. PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
  83. static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
  84. MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
  85. MUX_SEL_AUD, 0, 1),
  86. MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
  87. MUX_SEL_AUD, 4, 1),
  88. MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
  89. MUX_SEL_AUD, 8, 1),
  90. };
  91. static const struct samsung_div_clock aud_div_clks[] __initconst = {
  92. DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
  93. DIV_AUD0, 0, 4),
  94. DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
  95. DIV_AUD1, 0, 4),
  96. DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
  97. DIV_AUD1, 4, 8),
  98. DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
  99. DIV_AUD1, 12, 4),
  100. };
  101. static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
  102. GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
  103. EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
  104. GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
  105. EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
  106. GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
  107. EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
  108. GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
  109. 0, 0, 0),
  110. GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
  111. EN_IP_AUD, 1, 0, 0),
  112. GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
  113. GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
  114. GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
  115. EN_IP_AUD, 4, 0, 0),
  116. };
  117. static const struct samsung_cmu_info aud_cmu __initconst = {
  118. .mux_clks = aud_mux_clks,
  119. .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
  120. .div_clks = aud_div_clks,
  121. .nr_div_clks = ARRAY_SIZE(aud_div_clks),
  122. .gate_clks = aud_gate_clks,
  123. .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
  124. .nr_clk_ids = AUD_NR_CLK,
  125. .clk_regs = aud_clk_regs,
  126. .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
  127. };
  128. static void __init exynos5260_clk_aud_init(struct device_node *np)
  129. {
  130. samsung_cmu_register_one(np, &aud_cmu);
  131. }
  132. CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
  133. exynos5260_clk_aud_init);
  134. /* CMU_DISP */
  135. static const unsigned long disp_clk_regs[] __initconst = {
  136. MUX_SEL_DISP0,
  137. MUX_SEL_DISP1,
  138. MUX_SEL_DISP2,
  139. MUX_SEL_DISP3,
  140. MUX_SEL_DISP4,
  141. DIV_DISP,
  142. EN_ACLK_DISP,
  143. EN_PCLK_DISP,
  144. EN_SCLK_DISP0,
  145. EN_SCLK_DISP1,
  146. EN_IP_DISP,
  147. EN_IP_DISP_BUS,
  148. };
  149. PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
  150. "phyclk_dptx_phy_ch3_txd_clk"};
  151. PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
  152. "phyclk_dptx_phy_ch2_txd_clk"};
  153. PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
  154. "phyclk_dptx_phy_ch1_txd_clk"};
  155. PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
  156. "phyclk_dptx_phy_ch0_txd_clk"};
  157. PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
  158. PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
  159. PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
  160. PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
  161. "phyclk_hdmi_phy_tmds_clko"};
  162. PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
  163. "phyclk_hdmi_phy_ref_clko"};
  164. PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
  165. "phyclk_hdmi_phy_pixel_clko"};
  166. PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
  167. "phyclk_hdmi_link_o_tmds_clkhi"};
  168. PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
  169. "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
  170. PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
  171. "phyclk_dptx_phy_o_ref_clk_24m"};
  172. PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
  173. "phyclk_dptx_phy_clk_div2"};
  174. PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
  175. "mout_aclk_disp_222_user"};
  176. PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
  177. "phyclk_mipi_dphy_4l_m_rxclkesc0"};
  178. PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
  179. "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
  180. static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
  181. MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
  182. mout_aclk_disp_333_user_p,
  183. MUX_SEL_DISP0, 0, 1),
  184. MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
  185. mout_sclk_disp_pixel_user_p,
  186. MUX_SEL_DISP0, 4, 1),
  187. MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
  188. mout_aclk_disp_222_user_p,
  189. MUX_SEL_DISP0, 8, 1),
  190. MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
  191. "mout_phyclk_dptx_phy_ch0_txd_clk_user",
  192. mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
  193. MUX_SEL_DISP0, 16, 1),
  194. MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
  195. "mout_phyclk_dptx_phy_ch1_txd_clk_user",
  196. mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
  197. MUX_SEL_DISP0, 20, 1),
  198. MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
  199. "mout_phyclk_dptx_phy_ch2_txd_clk_user",
  200. mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
  201. MUX_SEL_DISP0, 24, 1),
  202. MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
  203. "mout_phyclk_dptx_phy_ch3_txd_clk_user",
  204. mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
  205. MUX_SEL_DISP0, 28, 1),
  206. MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
  207. "mout_phyclk_dptx_phy_clk_div2_user",
  208. mout_phyclk_dptx_phy_clk_div2_user_p,
  209. MUX_SEL_DISP1, 0, 1),
  210. MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
  211. "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
  212. mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
  213. MUX_SEL_DISP1, 4, 1),
  214. MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
  215. "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
  216. mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
  217. MUX_SEL_DISP1, 8, 1),
  218. MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
  219. "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
  220. mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
  221. MUX_SEL_DISP1, 16, 1),
  222. MUX(DISP_MOUT_HDMI_PHY_PIXEL,
  223. "mout_phyclk_hdmi_phy_pixel_clko_user",
  224. mout_phyclk_hdmi_phy_pixel_clko_user_p,
  225. MUX_SEL_DISP1, 20, 1),
  226. MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
  227. "mout_phyclk_hdmi_phy_ref_clko_user",
  228. mout_phyclk_hdmi_phy_ref_clko_user_p,
  229. MUX_SEL_DISP1, 24, 1),
  230. MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
  231. "mout_phyclk_hdmi_phy_tmds_clko_user",
  232. mout_phyclk_hdmi_phy_tmds_clko_user_p,
  233. MUX_SEL_DISP1, 28, 1),
  234. MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
  235. "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
  236. mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
  237. MUX_SEL_DISP2, 0, 1),
  238. MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
  239. mout_sclk_hdmi_pixel_p,
  240. MUX_SEL_DISP2, 4, 1),
  241. MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
  242. mout_sclk_hdmi_spdif_p,
  243. MUX_SEL_DISP4, 4, 2),
  244. };
  245. static const struct samsung_div_clock disp_div_clks[] __initconst = {
  246. DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
  247. "mout_aclk_disp_222_user",
  248. DIV_DISP, 8, 4),
  249. DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
  250. "mout_sclk_disp_pixel_user",
  251. DIV_DISP, 12, 4),
  252. DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
  253. "dout_sclk_hdmi_phy_pixel_clki",
  254. "mout_sclk_hdmi_pixel",
  255. DIV_DISP, 16, 4),
  256. };
  257. static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
  258. GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
  259. "mout_phyclk_hdmi_phy_pixel_clko_user",
  260. EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
  261. GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
  262. "dout_sclk_hdmi_phy_pixel_clki",
  263. EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
  264. GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
  265. EN_IP_DISP, 4, 0, 0),
  266. GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
  267. EN_IP_DISP, 5, 0, 0),
  268. GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
  269. EN_IP_DISP, 6, 0, 0),
  270. GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
  271. EN_IP_DISP, 7, 0, 0),
  272. GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
  273. EN_IP_DISP, 8, 0, 0),
  274. GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
  275. EN_IP_DISP, 9, 0, 0),
  276. GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
  277. EN_IP_DISP, 10, 0, 0),
  278. GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
  279. EN_IP_DISP, 11, 0, 0),
  280. GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
  281. EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
  282. GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
  283. EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
  284. GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
  285. "mout_aclk_disp_222_user",
  286. EN_IP_DISP, 22, 0, 0),
  287. GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
  288. "mout_aclk_disp_222_user",
  289. EN_IP_DISP, 23, 0, 0),
  290. GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
  291. EN_IP_DISP, 25, 0, 0),
  292. };
  293. static const struct samsung_cmu_info disp_cmu __initconst = {
  294. .mux_clks = disp_mux_clks,
  295. .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
  296. .div_clks = disp_div_clks,
  297. .nr_div_clks = ARRAY_SIZE(disp_div_clks),
  298. .gate_clks = disp_gate_clks,
  299. .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
  300. .nr_clk_ids = DISP_NR_CLK,
  301. .clk_regs = disp_clk_regs,
  302. .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
  303. };
  304. static void __init exynos5260_clk_disp_init(struct device_node *np)
  305. {
  306. samsung_cmu_register_one(np, &disp_cmu);
  307. }
  308. CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
  309. exynos5260_clk_disp_init);
  310. /* CMU_EGL */
  311. static const unsigned long egl_clk_regs[] __initconst = {
  312. EGL_PLL_LOCK,
  313. EGL_PLL_CON0,
  314. EGL_PLL_CON1,
  315. EGL_PLL_FREQ_DET,
  316. MUX_SEL_EGL,
  317. MUX_ENABLE_EGL,
  318. DIV_EGL,
  319. DIV_EGL_PLL_FDET,
  320. EN_ACLK_EGL,
  321. EN_PCLK_EGL,
  322. EN_SCLK_EGL,
  323. };
  324. PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
  325. PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
  326. static const struct samsung_mux_clock egl_mux_clks[] __initconst = {
  327. MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
  328. MUX_SEL_EGL, 4, 1),
  329. MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
  330. };
  331. static const struct samsung_div_clock egl_div_clks[] __initconst = {
  332. DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
  333. DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
  334. DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
  335. DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
  336. DIV_EGL, 12, 3),
  337. DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
  338. DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
  339. DIV_EGL, 20, 3),
  340. DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
  341. };
  342. static const struct samsung_pll_clock egl_pll_clks[] __initconst = {
  343. PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
  344. EGL_PLL_LOCK, EGL_PLL_CON0,
  345. pll2550_24mhz_tbl),
  346. };
  347. static const struct samsung_cmu_info egl_cmu __initconst = {
  348. .pll_clks = egl_pll_clks,
  349. .nr_pll_clks = ARRAY_SIZE(egl_pll_clks),
  350. .mux_clks = egl_mux_clks,
  351. .nr_mux_clks = ARRAY_SIZE(egl_mux_clks),
  352. .div_clks = egl_div_clks,
  353. .nr_div_clks = ARRAY_SIZE(egl_div_clks),
  354. .nr_clk_ids = EGL_NR_CLK,
  355. .clk_regs = egl_clk_regs,
  356. .nr_clk_regs = ARRAY_SIZE(egl_clk_regs),
  357. };
  358. static void __init exynos5260_clk_egl_init(struct device_node *np)
  359. {
  360. samsung_cmu_register_one(np, &egl_cmu);
  361. }
  362. CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
  363. exynos5260_clk_egl_init);
  364. /* CMU_FSYS */
  365. static const unsigned long fsys_clk_regs[] __initconst = {
  366. MUX_SEL_FSYS0,
  367. MUX_SEL_FSYS1,
  368. EN_ACLK_FSYS,
  369. EN_ACLK_FSYS_SECURE_RTIC,
  370. EN_ACLK_FSYS_SECURE_SMMU_RTIC,
  371. EN_SCLK_FSYS,
  372. EN_IP_FSYS,
  373. EN_IP_FSYS_SECURE_RTIC,
  374. EN_IP_FSYS_SECURE_SMMU_RTIC,
  375. };
  376. PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
  377. "phyclk_usbhost20_phy_phyclock"};
  378. PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
  379. "phyclk_usbhost20_phy_freeclk"};
  380. PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
  381. "phyclk_usbhost20_phy_clk48mohci"};
  382. PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
  383. "phyclk_usbdrd30_udrd30_pipe_pclk"};
  384. PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
  385. "phyclk_usbdrd30_udrd30_phyclock"};
  386. static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
  387. MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
  388. "mout_phyclk_usbdrd30_phyclock_user",
  389. mout_phyclk_usbdrd30_phyclock_user_p,
  390. MUX_SEL_FSYS1, 0, 1),
  391. MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
  392. "mout_phyclk_usbdrd30_pipe_pclk_user",
  393. mout_phyclk_usbdrd30_pipe_pclk_user_p,
  394. MUX_SEL_FSYS1, 4, 1),
  395. MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
  396. "mout_phyclk_usbhost20_clk48mohci_user",
  397. mout_phyclk_usbhost20_clk48mohci_user_p,
  398. MUX_SEL_FSYS1, 8, 1),
  399. MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
  400. "mout_phyclk_usbhost20_freeclk_user",
  401. mout_phyclk_usbhost20_freeclk_user_p,
  402. MUX_SEL_FSYS1, 12, 1),
  403. MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
  404. "mout_phyclk_usbhost20_phyclk_user",
  405. mout_phyclk_usbhost20_phyclk_user_p,
  406. MUX_SEL_FSYS1, 16, 1),
  407. };
  408. static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
  409. GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
  410. "mout_phyclk_usbdrd30_phyclock_user",
  411. EN_SCLK_FSYS, 1, 0, 0),
  412. GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
  413. "mout_phyclk_usbdrd30_phyclock_user",
  414. EN_SCLK_FSYS, 7, 0, 0),
  415. GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
  416. EN_IP_FSYS, 6, 0, 0),
  417. GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
  418. EN_IP_FSYS, 7, 0, 0),
  419. GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
  420. EN_IP_FSYS, 8, 0, 0),
  421. GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
  422. EN_IP_FSYS, 9, 0, 0),
  423. GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
  424. EN_IP_FSYS, 13, 0, 0),
  425. GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
  426. EN_IP_FSYS, 14, 0, 0),
  427. GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
  428. EN_IP_FSYS, 15, 0, 0),
  429. GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
  430. EN_IP_FSYS, 18, 0, 0),
  431. GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
  432. EN_IP_FSYS, 20, 0, 0),
  433. GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
  434. EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
  435. GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
  436. EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
  437. };
  438. static const struct samsung_cmu_info fsys_cmu __initconst = {
  439. .mux_clks = fsys_mux_clks,
  440. .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
  441. .gate_clks = fsys_gate_clks,
  442. .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
  443. .nr_clk_ids = FSYS_NR_CLK,
  444. .clk_regs = fsys_clk_regs,
  445. .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
  446. };
  447. static void __init exynos5260_clk_fsys_init(struct device_node *np)
  448. {
  449. samsung_cmu_register_one(np, &fsys_cmu);
  450. }
  451. CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
  452. exynos5260_clk_fsys_init);
  453. /* CMU_G2D */
  454. static const unsigned long g2d_clk_regs[] __initconst = {
  455. MUX_SEL_G2D,
  456. MUX_STAT_G2D,
  457. DIV_G2D,
  458. EN_ACLK_G2D,
  459. EN_ACLK_G2D_SECURE_SSS,
  460. EN_ACLK_G2D_SECURE_SLIM_SSS,
  461. EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
  462. EN_ACLK_G2D_SECURE_SMMU_SSS,
  463. EN_ACLK_G2D_SECURE_SMMU_MDMA,
  464. EN_ACLK_G2D_SECURE_SMMU_G2D,
  465. EN_PCLK_G2D,
  466. EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
  467. EN_PCLK_G2D_SECURE_SMMU_SSS,
  468. EN_PCLK_G2D_SECURE_SMMU_MDMA,
  469. EN_PCLK_G2D_SECURE_SMMU_G2D,
  470. EN_IP_G2D,
  471. EN_IP_G2D_SECURE_SSS,
  472. EN_IP_G2D_SECURE_SLIM_SSS,
  473. EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
  474. EN_IP_G2D_SECURE_SMMU_SSS,
  475. EN_IP_G2D_SECURE_SMMU_MDMA,
  476. EN_IP_G2D_SECURE_SMMU_G2D,
  477. };
  478. PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
  479. static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
  480. MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
  481. mout_aclk_g2d_333_user_p,
  482. MUX_SEL_G2D, 0, 1),
  483. };
  484. static const struct samsung_div_clock g2d_div_clks[] __initconst = {
  485. DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
  486. DIV_G2D, 0, 3),
  487. };
  488. static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
  489. GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
  490. EN_IP_G2D, 4, 0, 0),
  491. GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
  492. EN_IP_G2D, 5, 0, 0),
  493. GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
  494. EN_IP_G2D, 6, 0, 0),
  495. GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
  496. EN_IP_G2D, 16, 0, 0),
  497. GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
  498. EN_IP_G2D_SECURE_SSS, 17, 0, 0),
  499. GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
  500. EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
  501. GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
  502. "mout_aclk_g2d_333_user",
  503. EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
  504. GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
  505. EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
  506. GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
  507. EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
  508. GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
  509. EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
  510. };
  511. static const struct samsung_cmu_info g2d_cmu __initconst = {
  512. .mux_clks = g2d_mux_clks,
  513. .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
  514. .div_clks = g2d_div_clks,
  515. .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
  516. .gate_clks = g2d_gate_clks,
  517. .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
  518. .nr_clk_ids = G2D_NR_CLK,
  519. .clk_regs = g2d_clk_regs,
  520. .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
  521. };
  522. static void __init exynos5260_clk_g2d_init(struct device_node *np)
  523. {
  524. samsung_cmu_register_one(np, &g2d_cmu);
  525. }
  526. CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
  527. exynos5260_clk_g2d_init);
  528. /* CMU_G3D */
  529. static const unsigned long g3d_clk_regs[] __initconst = {
  530. G3D_PLL_LOCK,
  531. G3D_PLL_CON0,
  532. G3D_PLL_CON1,
  533. G3D_PLL_FDET,
  534. MUX_SEL_G3D,
  535. DIV_G3D,
  536. DIV_G3D_PLL_FDET,
  537. EN_ACLK_G3D,
  538. EN_PCLK_G3D,
  539. EN_SCLK_G3D,
  540. EN_IP_G3D,
  541. };
  542. PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
  543. static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
  544. MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
  545. MUX_SEL_G3D, 0, 1),
  546. };
  547. static const struct samsung_div_clock g3d_div_clks[] __initconst = {
  548. DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
  549. DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
  550. };
  551. static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
  552. GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
  553. GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
  554. EN_IP_G3D, 3, 0, 0),
  555. };
  556. static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
  557. PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
  558. G3D_PLL_LOCK, G3D_PLL_CON0,
  559. pll2550_24mhz_tbl),
  560. };
  561. static const struct samsung_cmu_info g3d_cmu __initconst = {
  562. .pll_clks = g3d_pll_clks,
  563. .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
  564. .mux_clks = g3d_mux_clks,
  565. .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
  566. .div_clks = g3d_div_clks,
  567. .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
  568. .gate_clks = g3d_gate_clks,
  569. .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
  570. .nr_clk_ids = G3D_NR_CLK,
  571. .clk_regs = g3d_clk_regs,
  572. .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
  573. };
  574. static void __init exynos5260_clk_g3d_init(struct device_node *np)
  575. {
  576. samsung_cmu_register_one(np, &g3d_cmu);
  577. }
  578. CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
  579. exynos5260_clk_g3d_init);
  580. /* CMU_GSCL */
  581. static const unsigned long gscl_clk_regs[] __initconst = {
  582. MUX_SEL_GSCL,
  583. DIV_GSCL,
  584. EN_ACLK_GSCL,
  585. EN_ACLK_GSCL_FIMC,
  586. EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
  587. EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
  588. EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
  589. EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
  590. EN_PCLK_GSCL,
  591. EN_PCLK_GSCL_FIMC,
  592. EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
  593. EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
  594. EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
  595. EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
  596. EN_SCLK_GSCL,
  597. EN_SCLK_GSCL_FIMC,
  598. EN_IP_GSCL,
  599. EN_IP_GSCL_FIMC,
  600. EN_IP_GSCL_SECURE_SMMU_GSCL0,
  601. EN_IP_GSCL_SECURE_SMMU_GSCL1,
  602. EN_IP_GSCL_SECURE_SMMU_MSCL0,
  603. EN_IP_GSCL_SECURE_SMMU_MSCL1,
  604. };
  605. PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
  606. PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
  607. PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
  608. PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
  609. static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
  610. MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
  611. mout_aclk_gscl_333_user_p,
  612. MUX_SEL_GSCL, 0, 1),
  613. MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
  614. mout_aclk_m2m_400_user_p,
  615. MUX_SEL_GSCL, 4, 1),
  616. MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
  617. mout_aclk_gscl_fimc_user_p,
  618. MUX_SEL_GSCL, 8, 1),
  619. MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
  620. MUX_SEL_GSCL, 24, 1),
  621. };
  622. static const struct samsung_div_clock gscl_div_clks[] __initconst = {
  623. DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
  624. "mout_aclk_m2m_400_user",
  625. DIV_GSCL, 0, 3),
  626. DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
  627. "mout_aclk_m2m_400_user",
  628. DIV_GSCL, 4, 3),
  629. };
  630. static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
  631. GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
  632. EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
  633. GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
  634. EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
  635. GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
  636. EN_IP_GSCL, 2, 0, 0),
  637. GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
  638. EN_IP_GSCL, 3, 0, 0),
  639. GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
  640. EN_IP_GSCL, 4, 0, 0),
  641. GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
  642. EN_IP_GSCL, 5, 0, 0),
  643. GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
  644. "mout_aclk_gscl_333_user",
  645. EN_IP_GSCL, 8, 0, 0),
  646. GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
  647. "mout_aclk_gscl_333_user",
  648. EN_IP_GSCL, 9, 0, 0),
  649. GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
  650. "mout_aclk_gscl_fimc_user",
  651. EN_IP_GSCL_FIMC, 5, 0, 0),
  652. GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
  653. "mout_aclk_gscl_fimc_user",
  654. EN_IP_GSCL_FIMC, 6, 0, 0),
  655. GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
  656. "mout_aclk_gscl_fimc_user",
  657. EN_IP_GSCL_FIMC, 7, 0, 0),
  658. GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
  659. EN_IP_GSCL_FIMC, 8, 0, 0),
  660. GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
  661. EN_IP_GSCL_FIMC, 9, 0, 0),
  662. GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
  663. "mout_aclk_gscl_fimc_user",
  664. EN_IP_GSCL_FIMC, 10, 0, 0),
  665. GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
  666. "mout_aclk_gscl_fimc_user",
  667. EN_IP_GSCL_FIMC, 11, 0, 0),
  668. GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
  669. "mout_aclk_gscl_fimc_user",
  670. EN_IP_GSCL_FIMC, 12, 0, 0),
  671. GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
  672. "mout_aclk_gscl_333_user",
  673. EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
  674. GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
  675. EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
  676. GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
  677. "mout_aclk_m2m_400_user",
  678. EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
  679. GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
  680. "mout_aclk_m2m_400_user",
  681. EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
  682. };
  683. static const struct samsung_cmu_info gscl_cmu __initconst = {
  684. .mux_clks = gscl_mux_clks,
  685. .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
  686. .div_clks = gscl_div_clks,
  687. .nr_div_clks = ARRAY_SIZE(gscl_div_clks),
  688. .gate_clks = gscl_gate_clks,
  689. .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
  690. .nr_clk_ids = GSCL_NR_CLK,
  691. .clk_regs = gscl_clk_regs,
  692. .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
  693. };
  694. static void __init exynos5260_clk_gscl_init(struct device_node *np)
  695. {
  696. samsung_cmu_register_one(np, &gscl_cmu);
  697. }
  698. CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
  699. exynos5260_clk_gscl_init);
  700. /* CMU_ISP */
  701. static const unsigned long isp_clk_regs[] __initconst = {
  702. MUX_SEL_ISP0,
  703. MUX_SEL_ISP1,
  704. DIV_ISP,
  705. EN_ACLK_ISP0,
  706. EN_ACLK_ISP1,
  707. EN_PCLK_ISP0,
  708. EN_PCLK_ISP1,
  709. EN_SCLK_ISP,
  710. EN_IP_ISP0,
  711. EN_IP_ISP1,
  712. };
  713. PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
  714. PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"};
  715. static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
  716. MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
  717. MUX_SEL_ISP0, 0, 1),
  718. MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
  719. MUX_SEL_ISP0, 4, 1),
  720. };
  721. static const struct samsung_div_clock isp_div_clks[] __initconst = {
  722. DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
  723. DIV_ISP, 0, 3),
  724. DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
  725. DIV_ISP, 4, 4),
  726. DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
  727. DIV_ISP, 12, 3),
  728. DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
  729. DIV_ISP, 16, 4),
  730. DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
  731. };
  732. static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
  733. GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
  734. EN_IP_ISP0, 15, 0, 0),
  735. GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
  736. EN_IP_ISP1, 1, 0, 0),
  737. GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
  738. EN_IP_ISP1, 2, 0, 0),
  739. GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
  740. EN_IP_ISP1, 3, 0, 0),
  741. GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
  742. EN_IP_ISP1, 4, 0, 0),
  743. GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
  744. "mout_aclk_isp1_266",
  745. EN_IP_ISP1, 5, 0, 0),
  746. GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
  747. "mout_aclk_isp1_266",
  748. EN_IP_ISP1, 6, 0, 0),
  749. GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
  750. EN_IP_ISP1, 7, 0, 0),
  751. GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
  752. EN_IP_ISP1, 8, 0, 0),
  753. GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
  754. EN_IP_ISP1, 9, 0, 0),
  755. GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
  756. EN_IP_ISP1, 10, 0, 0),
  757. GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
  758. EN_IP_ISP1, 11, 0, 0),
  759. GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
  760. EN_IP_ISP1, 14, 0, 0),
  761. GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
  762. EN_IP_ISP1, 21, 0, 0),
  763. GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
  764. EN_IP_ISP1, 22, 0, 0),
  765. GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
  766. EN_IP_ISP1, 23, 0, 0),
  767. GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
  768. EN_IP_ISP1, 24, 0, 0),
  769. GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
  770. "mout_aclk_isp1_266",
  771. EN_IP_ISP1, 25, 0, 0),
  772. GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
  773. "mout_aclk_isp1_266",
  774. EN_IP_ISP1, 26, 0, 0),
  775. GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
  776. EN_IP_ISP1, 27, 0, 0),
  777. GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
  778. EN_IP_ISP1, 28, 0, 0),
  779. GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
  780. EN_IP_ISP1, 31, 0, 0),
  781. GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
  782. EN_IP_ISP1, 30, 0, 0),
  783. GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
  784. EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
  785. GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
  786. EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
  787. GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
  788. EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
  789. };
  790. static const struct samsung_cmu_info isp_cmu __initconst = {
  791. .mux_clks = isp_mux_clks,
  792. .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
  793. .div_clks = isp_div_clks,
  794. .nr_div_clks = ARRAY_SIZE(isp_div_clks),
  795. .gate_clks = isp_gate_clks,
  796. .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
  797. .nr_clk_ids = ISP_NR_CLK,
  798. .clk_regs = isp_clk_regs,
  799. .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
  800. };
  801. static void __init exynos5260_clk_isp_init(struct device_node *np)
  802. {
  803. samsung_cmu_register_one(np, &isp_cmu);
  804. }
  805. CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
  806. exynos5260_clk_isp_init);
  807. /* CMU_KFC */
  808. static const unsigned long kfc_clk_regs[] __initconst = {
  809. KFC_PLL_LOCK,
  810. KFC_PLL_CON0,
  811. KFC_PLL_CON1,
  812. KFC_PLL_FDET,
  813. MUX_SEL_KFC0,
  814. MUX_SEL_KFC2,
  815. DIV_KFC,
  816. DIV_KFC_PLL_FDET,
  817. EN_ACLK_KFC,
  818. EN_PCLK_KFC,
  819. EN_SCLK_KFC,
  820. EN_IP_KFC,
  821. };
  822. PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
  823. PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"};
  824. static const struct samsung_mux_clock kfc_mux_clks[] __initconst = {
  825. MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
  826. MUX_SEL_KFC0, 0, 1),
  827. MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
  828. };
  829. static const struct samsung_div_clock kfc_div_clks[] __initconst = {
  830. DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
  831. DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
  832. DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
  833. DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
  834. DIV_KFC, 12, 3),
  835. DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
  836. DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
  837. DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
  838. };
  839. static const struct samsung_pll_clock kfc_pll_clks[] __initconst = {
  840. PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
  841. KFC_PLL_LOCK, KFC_PLL_CON0,
  842. pll2550_24mhz_tbl),
  843. };
  844. static const struct samsung_cmu_info kfc_cmu __initconst = {
  845. .pll_clks = kfc_pll_clks,
  846. .nr_pll_clks = ARRAY_SIZE(kfc_pll_clks),
  847. .mux_clks = kfc_mux_clks,
  848. .nr_mux_clks = ARRAY_SIZE(kfc_mux_clks),
  849. .div_clks = kfc_div_clks,
  850. .nr_div_clks = ARRAY_SIZE(kfc_div_clks),
  851. .nr_clk_ids = KFC_NR_CLK,
  852. .clk_regs = kfc_clk_regs,
  853. .nr_clk_regs = ARRAY_SIZE(kfc_clk_regs),
  854. };
  855. static void __init exynos5260_clk_kfc_init(struct device_node *np)
  856. {
  857. samsung_cmu_register_one(np, &kfc_cmu);
  858. }
  859. CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
  860. exynos5260_clk_kfc_init);
  861. /* CMU_MFC */
  862. static const unsigned long mfc_clk_regs[] __initconst = {
  863. MUX_SEL_MFC,
  864. DIV_MFC,
  865. EN_ACLK_MFC,
  866. EN_ACLK_SECURE_SMMU2_MFC,
  867. EN_PCLK_MFC,
  868. EN_PCLK_SECURE_SMMU2_MFC,
  869. EN_IP_MFC,
  870. EN_IP_MFC_SECURE_SMMU2_MFC,
  871. };
  872. PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
  873. static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
  874. MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
  875. mout_aclk_mfc_333_user_p,
  876. MUX_SEL_MFC, 0, 1),
  877. };
  878. static const struct samsung_div_clock mfc_div_clks[] __initconst = {
  879. DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
  880. DIV_MFC, 0, 3),
  881. };
  882. static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
  883. GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
  884. EN_IP_MFC, 1, 0, 0),
  885. GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
  886. EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
  887. GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
  888. EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
  889. };
  890. static const struct samsung_cmu_info mfc_cmu __initconst = {
  891. .mux_clks = mfc_mux_clks,
  892. .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
  893. .div_clks = mfc_div_clks,
  894. .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
  895. .gate_clks = mfc_gate_clks,
  896. .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
  897. .nr_clk_ids = MFC_NR_CLK,
  898. .clk_regs = mfc_clk_regs,
  899. .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
  900. };
  901. static void __init exynos5260_clk_mfc_init(struct device_node *np)
  902. {
  903. samsung_cmu_register_one(np, &mfc_cmu);
  904. }
  905. CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
  906. exynos5260_clk_mfc_init);
  907. /* CMU_MIF */
  908. static const unsigned long mif_clk_regs[] __initconst = {
  909. MEM_PLL_LOCK,
  910. BUS_PLL_LOCK,
  911. MEDIA_PLL_LOCK,
  912. MEM_PLL_CON0,
  913. MEM_PLL_CON1,
  914. MEM_PLL_FDET,
  915. BUS_PLL_CON0,
  916. BUS_PLL_CON1,
  917. BUS_PLL_FDET,
  918. MEDIA_PLL_CON0,
  919. MEDIA_PLL_CON1,
  920. MEDIA_PLL_FDET,
  921. MUX_SEL_MIF,
  922. DIV_MIF,
  923. DIV_MIF_PLL_FDET,
  924. EN_ACLK_MIF,
  925. EN_ACLK_MIF_SECURE_DREX1_TZ,
  926. EN_ACLK_MIF_SECURE_DREX0_TZ,
  927. EN_ACLK_MIF_SECURE_INTMEM,
  928. EN_PCLK_MIF,
  929. EN_PCLK_MIF_SECURE_MONOCNT,
  930. EN_PCLK_MIF_SECURE_RTC_APBIF,
  931. EN_PCLK_MIF_SECURE_DREX1_TZ,
  932. EN_PCLK_MIF_SECURE_DREX0_TZ,
  933. EN_SCLK_MIF,
  934. EN_IP_MIF,
  935. EN_IP_MIF_SECURE_MONOCNT,
  936. EN_IP_MIF_SECURE_RTC_APBIF,
  937. EN_IP_MIF_SECURE_DREX1_TZ,
  938. EN_IP_MIF_SECURE_DREX0_TZ,
  939. EN_IP_MIF_SECURE_INTEMEM,
  940. };
  941. PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
  942. PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
  943. PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
  944. PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
  945. PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
  946. PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
  947. PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
  948. static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
  949. MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
  950. MUX_SEL_MIF, 0, 1),
  951. MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
  952. MUX_SEL_MIF, 4, 1),
  953. MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
  954. MUX_SEL_MIF, 8, 1),
  955. MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
  956. MUX_SEL_MIF, 12, 1),
  957. MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
  958. MUX_SEL_MIF, 16, 1),
  959. MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
  960. MUX_SEL_MIF, 20, 1),
  961. MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
  962. MUX_SEL_MIF, 24, 1),
  963. };
  964. static const struct samsung_div_clock mif_div_clks[] __initconst = {
  965. DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
  966. DIV_MIF, 0, 3),
  967. DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
  968. DIV_MIF, 4, 3),
  969. DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
  970. DIV_MIF, 8, 3),
  971. DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
  972. DIV_MIF, 12, 3),
  973. DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
  974. DIV_MIF, 16, 4),
  975. DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
  976. DIV_MIF, 20, 3),
  977. DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
  978. DIV_MIF, 24, 3),
  979. DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
  980. DIV_MIF, 28, 4),
  981. };
  982. static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
  983. GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
  984. EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
  985. GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
  986. EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
  987. GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
  988. EN_IP_MIF_SECURE_MONOCNT, 22,
  989. CLK_IGNORE_UNUSED, 0),
  990. GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
  991. EN_IP_MIF_SECURE_RTC_APBIF, 23,
  992. CLK_IGNORE_UNUSED, 0),
  993. GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
  994. EN_IP_MIF_SECURE_DREX1_TZ, 9,
  995. CLK_IGNORE_UNUSED, 0),
  996. GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
  997. EN_IP_MIF_SECURE_DREX0_TZ, 9,
  998. CLK_IGNORE_UNUSED, 0),
  999. GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
  1000. EN_IP_MIF_SECURE_INTEMEM, 11,
  1001. CLK_IGNORE_UNUSED, 0),
  1002. GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
  1003. "dout_clkm_phy", EN_SCLK_MIF, 0,
  1004. CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
  1005. GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
  1006. "dout_clkm_phy", EN_SCLK_MIF, 1,
  1007. CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
  1008. };
  1009. static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
  1010. PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
  1011. MEM_PLL_LOCK, MEM_PLL_CON0,
  1012. pll2550_24mhz_tbl),
  1013. PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
  1014. BUS_PLL_LOCK, BUS_PLL_CON0,
  1015. pll2550_24mhz_tbl),
  1016. PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
  1017. MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
  1018. pll2550_24mhz_tbl),
  1019. };
  1020. static const struct samsung_cmu_info mif_cmu __initconst = {
  1021. .pll_clks = mif_pll_clks,
  1022. .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
  1023. .mux_clks = mif_mux_clks,
  1024. .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
  1025. .div_clks = mif_div_clks,
  1026. .nr_div_clks = ARRAY_SIZE(mif_div_clks),
  1027. .gate_clks = mif_gate_clks,
  1028. .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
  1029. .nr_clk_ids = MIF_NR_CLK,
  1030. .clk_regs = mif_clk_regs,
  1031. .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
  1032. };
  1033. static void __init exynos5260_clk_mif_init(struct device_node *np)
  1034. {
  1035. samsung_cmu_register_one(np, &mif_cmu);
  1036. }
  1037. CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
  1038. exynos5260_clk_mif_init);
  1039. /* CMU_PERI */
  1040. static const unsigned long peri_clk_regs[] __initconst = {
  1041. MUX_SEL_PERI,
  1042. MUX_SEL_PERI1,
  1043. DIV_PERI,
  1044. EN_PCLK_PERI0,
  1045. EN_PCLK_PERI1,
  1046. EN_PCLK_PERI2,
  1047. EN_PCLK_PERI3,
  1048. EN_PCLK_PERI_SECURE_CHIPID,
  1049. EN_PCLK_PERI_SECURE_PROVKEY0,
  1050. EN_PCLK_PERI_SECURE_PROVKEY1,
  1051. EN_PCLK_PERI_SECURE_SECKEY,
  1052. EN_PCLK_PERI_SECURE_ANTIRBKCNT,
  1053. EN_PCLK_PERI_SECURE_TOP_RTC,
  1054. EN_PCLK_PERI_SECURE_TZPC,
  1055. EN_SCLK_PERI,
  1056. EN_SCLK_PERI_SECURE_TOP_RTC,
  1057. EN_IP_PERI0,
  1058. EN_IP_PERI1,
  1059. EN_IP_PERI2,
  1060. EN_IP_PERI_SECURE_CHIPID,
  1061. EN_IP_PERI_SECURE_PROVKEY0,
  1062. EN_IP_PERI_SECURE_PROVKEY1,
  1063. EN_IP_PERI_SECURE_SECKEY,
  1064. EN_IP_PERI_SECURE_ANTIRBKCNT,
  1065. EN_IP_PERI_SECURE_TOP_RTC,
  1066. EN_IP_PERI_SECURE_TZPC,
  1067. };
  1068. PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
  1069. "phyclk_hdmi_phy_ref_cko"};
  1070. PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
  1071. "phyclk_hdmi_phy_ref_cko"};
  1072. PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
  1073. "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
  1074. static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
  1075. MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
  1076. MUX_SEL_PERI1, 4, 2),
  1077. MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
  1078. MUX_SEL_PERI1, 12, 2),
  1079. MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
  1080. MUX_SEL_PERI1, 20, 2),
  1081. };
  1082. static const struct samsung_div_clock peri_div_clks[] __initconst = {
  1083. DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
  1084. DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
  1085. };
  1086. static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
  1087. GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
  1088. CLK_SET_RATE_PARENT, 0),
  1089. GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
  1090. CLK_SET_RATE_PARENT, 0),
  1091. GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
  1092. EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
  1093. GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
  1094. EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
  1095. GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
  1096. EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
  1097. GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
  1098. EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
  1099. GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
  1100. EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
  1101. GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
  1102. EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
  1103. GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
  1104. EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
  1105. GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
  1106. EN_IP_PERI0, 1, 0, 0),
  1107. GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
  1108. EN_IP_PERI0, 5, 0, 0),
  1109. GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
  1110. EN_IP_PERI0, 6, 0, 0),
  1111. GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
  1112. EN_IP_PERI0, 7, 0, 0),
  1113. GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
  1114. EN_IP_PERI0, 8, 0, 0),
  1115. GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
  1116. EN_IP_PERI0, 9, 0, 0),
  1117. GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
  1118. EN_IP_PERI0, 10, 0, 0),
  1119. GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
  1120. EN_IP_PERI0, 11, 0, 0),
  1121. GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
  1122. EN_IP_PERI0, 12, 0, 0),
  1123. GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
  1124. EN_IP_PERI0, 13, 0, 0),
  1125. GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
  1126. EN_IP_PERI0, 14, 0, 0),
  1127. GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
  1128. EN_IP_PERI0, 15, 0, 0),
  1129. GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
  1130. EN_IP_PERI0, 16, 0, 0),
  1131. GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
  1132. EN_IP_PERI0, 17, 0, 0),
  1133. GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
  1134. EN_IP_PERI0, 18, 0, 0),
  1135. GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
  1136. EN_IP_PERI0, 20, 0, 0),
  1137. GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
  1138. EN_IP_PERI0, 21, 0, 0),
  1139. GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
  1140. EN_IP_PERI0, 22, 0, 0),
  1141. GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
  1142. EN_IP_PERI0, 23, 0, 0),
  1143. GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
  1144. EN_IP_PERI0, 24, 0, 0),
  1145. GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
  1146. EN_IP_PERI0, 25, 0, 0),
  1147. GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
  1148. EN_IP_PERI2, 0, 0, 0),
  1149. GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
  1150. EN_IP_PERI2, 3, 0, 0),
  1151. GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
  1152. EN_IP_PERI2, 6, 0, 0),
  1153. GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
  1154. EN_IP_PERI2, 7, 0, 0),
  1155. GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
  1156. EN_IP_PERI2, 8, 0, 0),
  1157. GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
  1158. EN_IP_PERI2, 9, 0, 0),
  1159. GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
  1160. EN_IP_PERI2, 10, 0, 0),
  1161. GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
  1162. EN_IP_PERI2, 11, 0, 0),
  1163. GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
  1164. EN_IP_PERI2, 12, 0, 0),
  1165. GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
  1166. EN_IP_PERI2, 13, 0, 0),
  1167. GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
  1168. EN_IP_PERI2, 14, 0, 0),
  1169. GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
  1170. EN_IP_PERI2, 18, 0, 0),
  1171. GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
  1172. EN_IP_PERI2, 19, 0, 0),
  1173. GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
  1174. EN_IP_PERI2, 20, 0, 0),
  1175. GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
  1176. EN_IP_PERI2, 21, 0, 0),
  1177. GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
  1178. EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
  1179. GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
  1180. EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
  1181. GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
  1182. EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
  1183. GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
  1184. EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
  1185. GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
  1186. EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
  1187. GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
  1188. EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
  1189. GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
  1190. EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
  1191. GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
  1192. EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
  1193. GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
  1194. EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
  1195. GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
  1196. EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
  1197. GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
  1198. EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
  1199. GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
  1200. EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
  1201. GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
  1202. EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
  1203. GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
  1204. EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
  1205. GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
  1206. EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
  1207. GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
  1208. EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
  1209. };
  1210. static const struct samsung_cmu_info peri_cmu __initconst = {
  1211. .mux_clks = peri_mux_clks,
  1212. .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
  1213. .div_clks = peri_div_clks,
  1214. .nr_div_clks = ARRAY_SIZE(peri_div_clks),
  1215. .gate_clks = peri_gate_clks,
  1216. .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
  1217. .nr_clk_ids = PERI_NR_CLK,
  1218. .clk_regs = peri_clk_regs,
  1219. .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
  1220. };
  1221. static void __init exynos5260_clk_peri_init(struct device_node *np)
  1222. {
  1223. samsung_cmu_register_one(np, &peri_cmu);
  1224. }
  1225. CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
  1226. exynos5260_clk_peri_init);
  1227. /* CMU_TOP */
  1228. static const unsigned long top_clk_regs[] __initconst = {
  1229. DISP_PLL_LOCK,
  1230. AUD_PLL_LOCK,
  1231. DISP_PLL_CON0,
  1232. DISP_PLL_CON1,
  1233. DISP_PLL_FDET,
  1234. AUD_PLL_CON0,
  1235. AUD_PLL_CON1,
  1236. AUD_PLL_CON2,
  1237. AUD_PLL_FDET,
  1238. MUX_SEL_TOP_PLL0,
  1239. MUX_SEL_TOP_MFC,
  1240. MUX_SEL_TOP_G2D,
  1241. MUX_SEL_TOP_GSCL,
  1242. MUX_SEL_TOP_ISP10,
  1243. MUX_SEL_TOP_ISP11,
  1244. MUX_SEL_TOP_DISP0,
  1245. MUX_SEL_TOP_DISP1,
  1246. MUX_SEL_TOP_BUS,
  1247. MUX_SEL_TOP_PERI0,
  1248. MUX_SEL_TOP_PERI1,
  1249. MUX_SEL_TOP_FSYS,
  1250. DIV_TOP_G2D_MFC,
  1251. DIV_TOP_GSCL_ISP0,
  1252. DIV_TOP_ISP10,
  1253. DIV_TOP_ISP11,
  1254. DIV_TOP_DISP,
  1255. DIV_TOP_BUS,
  1256. DIV_TOP_PERI0,
  1257. DIV_TOP_PERI1,
  1258. DIV_TOP_PERI2,
  1259. DIV_TOP_FSYS0,
  1260. DIV_TOP_FSYS1,
  1261. DIV_TOP_HPM,
  1262. DIV_TOP_PLL_FDET,
  1263. EN_ACLK_TOP,
  1264. EN_SCLK_TOP,
  1265. EN_IP_TOP,
  1266. };
  1267. /* fixed rate clocks generated inside the soc */
  1268. static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
  1269. FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
  1270. 0, 270000000),
  1271. FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
  1272. 0, 270000000),
  1273. FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
  1274. 0, 270000000),
  1275. FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
  1276. 0, 270000000),
  1277. FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
  1278. 0, 250000000),
  1279. FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
  1280. 0, 1660000000),
  1281. FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
  1282. NULL, 0, 125000000),
  1283. FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
  1284. "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
  1285. 0, 187500000),
  1286. FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
  1287. NULL, 0, 24000000),
  1288. FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
  1289. 0, 135000000),
  1290. FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
  1291. "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000),
  1292. FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
  1293. NULL, 0, 60000000),
  1294. FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
  1295. NULL, 0, 60000000),
  1296. FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
  1297. "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000),
  1298. FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
  1299. "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000),
  1300. FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
  1301. "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000),
  1302. };
  1303. PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
  1304. PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
  1305. PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
  1306. PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
  1307. PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
  1308. PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
  1309. PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
  1310. PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
  1311. PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
  1312. PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
  1313. PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
  1314. PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
  1315. "mout_gscl_bustop_333"};
  1316. PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
  1317. PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
  1318. "mout_m2m_mediatop_400"};
  1319. PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
  1320. PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
  1321. "mout_gscl_bustop_fimc"};
  1322. PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
  1323. "mout_memtop_pll_user"};
  1324. PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
  1325. PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
  1326. PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
  1327. PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
  1328. PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
  1329. PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
  1330. PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
  1331. PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
  1332. PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
  1333. PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
  1334. PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
  1335. "mout_bustop_pll_user"};
  1336. PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
  1337. PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
  1338. PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
  1339. PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
  1340. PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
  1341. PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
  1342. PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
  1343. PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
  1344. "mout_mediatop_pll_user"};
  1345. PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
  1346. "mout_mediatop_pll_user"};
  1347. PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
  1348. "mout_mediatop_pll_user"};
  1349. static const struct samsung_mux_clock top_mux_clks[] __initconst = {
  1350. MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
  1351. mout_mediatop_pll_user_p,
  1352. MUX_SEL_TOP_PLL0, 0, 1),
  1353. MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
  1354. mout_memtop_pll_user_p,
  1355. MUX_SEL_TOP_PLL0, 4, 1),
  1356. MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
  1357. mout_bustop_pll_user_p,
  1358. MUX_SEL_TOP_PLL0, 8, 1),
  1359. MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
  1360. MUX_SEL_TOP_PLL0, 12, 1),
  1361. MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
  1362. MUX_SEL_TOP_PLL0, 16, 1),
  1363. MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
  1364. mout_audtop_pll_user_p,
  1365. MUX_SEL_TOP_PLL0, 24, 1),
  1366. MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
  1367. MUX_SEL_TOP_DISP0, 0, 1),
  1368. MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
  1369. MUX_SEL_TOP_DISP0, 8, 1),
  1370. MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
  1371. MUX_SEL_TOP_DISP0, 12, 1),
  1372. MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
  1373. MUX_SEL_TOP_DISP0, 20, 1),
  1374. MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
  1375. MUX_SEL_TOP_DISP1, 0, 1),
  1376. MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
  1377. mout_disp_media_pixel_p,
  1378. MUX_SEL_TOP_DISP1, 8, 1),
  1379. MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
  1380. mout_sclk_peri_spi_clk_p,
  1381. MUX_SEL_TOP_PERI1, 0, 1),
  1382. MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
  1383. mout_sclk_peri_spi_clk_p,
  1384. MUX_SEL_TOP_PERI1, 4, 1),
  1385. MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
  1386. mout_sclk_peri_spi_clk_p,
  1387. MUX_SEL_TOP_PERI1, 8, 1),
  1388. MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
  1389. mout_sclk_peri_uart_uclk_p,
  1390. MUX_SEL_TOP_PERI1, 12, 1),
  1391. MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
  1392. mout_sclk_peri_uart_uclk_p,
  1393. MUX_SEL_TOP_PERI1, 16, 1),
  1394. MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
  1395. mout_sclk_peri_uart_uclk_p,
  1396. MUX_SEL_TOP_PERI1, 20, 1),
  1397. MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
  1398. mout_bus_bustop_400_p,
  1399. MUX_SEL_TOP_BUS, 0, 1),
  1400. MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
  1401. mout_bus_bustop_100_p,
  1402. MUX_SEL_TOP_BUS, 4, 1),
  1403. MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
  1404. mout_bus_bustop_100_p,
  1405. MUX_SEL_TOP_BUS, 8, 1),
  1406. MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
  1407. mout_bus_bustop_400_p,
  1408. MUX_SEL_TOP_BUS, 12, 1),
  1409. MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
  1410. mout_bus_bustop_400_p,
  1411. MUX_SEL_TOP_BUS, 16, 1),
  1412. MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
  1413. mout_bus_bustop_100_p,
  1414. MUX_SEL_TOP_BUS, 20, 1),
  1415. MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
  1416. mout_bus_bustop_400_p,
  1417. MUX_SEL_TOP_BUS, 24, 1),
  1418. MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
  1419. mout_bus_bustop_100_p,
  1420. MUX_SEL_TOP_BUS, 28, 1),
  1421. MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
  1422. mout_sclk_fsys_usb_p,
  1423. MUX_SEL_TOP_FSYS, 0, 1),
  1424. MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
  1425. mout_sclk_fsys_mmc_sdclkin_a_p,
  1426. MUX_SEL_TOP_FSYS, 4, 1),
  1427. MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
  1428. mout_sclk_fsys_mmc2_sdclkin_b_p,
  1429. MUX_SEL_TOP_FSYS, 8, 1),
  1430. MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
  1431. mout_sclk_fsys_mmc_sdclkin_a_p,
  1432. MUX_SEL_TOP_FSYS, 12, 1),
  1433. MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
  1434. mout_sclk_fsys_mmc1_sdclkin_b_p,
  1435. MUX_SEL_TOP_FSYS, 16, 1),
  1436. MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
  1437. mout_sclk_fsys_mmc_sdclkin_a_p,
  1438. MUX_SEL_TOP_FSYS, 20, 1),
  1439. MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
  1440. mout_sclk_fsys_mmc0_sdclkin_b_p,
  1441. MUX_SEL_TOP_FSYS, 24, 1),
  1442. MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
  1443. mout_isp1_media_400_p,
  1444. MUX_SEL_TOP_ISP10, 4, 1),
  1445. MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
  1446. MUX_SEL_TOP_ISP10, 8 , 1),
  1447. MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
  1448. mout_isp1_media_266_p,
  1449. MUX_SEL_TOP_ISP10, 16, 1),
  1450. MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
  1451. MUX_SEL_TOP_ISP10, 20, 1),
  1452. MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
  1453. MUX_SEL_TOP_ISP11, 4, 1),
  1454. MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
  1455. MUX_SEL_TOP_ISP11, 8, 1),
  1456. MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
  1457. mout_sclk_isp_uart_p,
  1458. MUX_SEL_TOP_ISP11, 12, 1),
  1459. MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
  1460. mout_sclk_isp_sensor_p,
  1461. MUX_SEL_TOP_ISP11, 16, 1),
  1462. MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
  1463. mout_sclk_isp_sensor_p,
  1464. MUX_SEL_TOP_ISP11, 20, 1),
  1465. MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
  1466. mout_sclk_isp_sensor_p,
  1467. MUX_SEL_TOP_ISP11, 24, 1),
  1468. MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
  1469. mout_mfc_bustop_333_p,
  1470. MUX_SEL_TOP_MFC, 4, 1),
  1471. MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
  1472. MUX_SEL_TOP_MFC, 8, 1),
  1473. MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
  1474. mout_g2d_bustop_333_p,
  1475. MUX_SEL_TOP_G2D, 4, 1),
  1476. MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
  1477. MUX_SEL_TOP_G2D, 8, 1),
  1478. MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
  1479. mout_m2m_mediatop_400_p,
  1480. MUX_SEL_TOP_GSCL, 0, 1),
  1481. MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
  1482. mout_aclk_gscl_400_p,
  1483. MUX_SEL_TOP_GSCL, 4, 1),
  1484. MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
  1485. mout_gscl_bustop_333_p,
  1486. MUX_SEL_TOP_GSCL, 8, 1),
  1487. MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
  1488. mout_aclk_gscl_333_p,
  1489. MUX_SEL_TOP_GSCL, 12, 1),
  1490. MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
  1491. mout_gscl_bustop_fimc_p,
  1492. MUX_SEL_TOP_GSCL, 16, 1),
  1493. MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
  1494. mout_aclk_gscl_fimc_p,
  1495. MUX_SEL_TOP_GSCL, 20, 1),
  1496. };
  1497. static const struct samsung_div_clock top_div_clks[] __initconst = {
  1498. DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
  1499. DIV_TOP_G2D_MFC, 0, 3),
  1500. DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
  1501. DIV_TOP_G2D_MFC, 4, 3),
  1502. DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
  1503. DIV_TOP_GSCL_ISP0, 0, 3),
  1504. DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
  1505. DIV_TOP_GSCL_ISP0, 4, 3),
  1506. DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
  1507. "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
  1508. DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
  1509. "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
  1510. DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
  1511. "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
  1512. DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
  1513. "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
  1514. DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
  1515. DIV_TOP_ISP10, 0, 3),
  1516. DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
  1517. DIV_TOP_ISP10, 4, 3),
  1518. DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
  1519. "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
  1520. DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
  1521. "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
  1522. DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
  1523. "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
  1524. DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
  1525. "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
  1526. DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
  1527. "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
  1528. DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
  1529. "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
  1530. DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
  1531. "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
  1532. DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
  1533. "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
  1534. DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
  1535. "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
  1536. DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
  1537. DIV_TOP_DISP, 0, 3),
  1538. DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
  1539. DIV_TOP_DISP, 4, 3),
  1540. DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
  1541. "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
  1542. DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
  1543. "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
  1544. DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
  1545. "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
  1546. DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
  1547. "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
  1548. DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
  1549. "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
  1550. DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
  1551. "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
  1552. DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
  1553. "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
  1554. DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
  1555. "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
  1556. DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
  1557. "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
  1558. DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
  1559. "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
  1560. DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
  1561. "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
  1562. DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
  1563. "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
  1564. DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
  1565. "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
  1566. DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
  1567. "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
  1568. DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
  1569. "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
  1570. DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
  1571. "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
  1572. DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
  1573. "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
  1574. DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
  1575. "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
  1576. DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
  1577. DIV_TOP_PERI2, 20, 4),
  1578. DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
  1579. "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
  1580. DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
  1581. "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
  1582. DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
  1583. "dout_sclk_fsys_usbdrd30_suspend_clk",
  1584. "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
  1585. DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
  1586. "mout_sclk_fsys_mmc0_sdclkin_b",
  1587. DIV_TOP_FSYS0, 12, 4),
  1588. DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
  1589. "dout_sclk_fsys_mmc0_sdclkin_a",
  1590. DIV_TOP_FSYS0, 16, 8),
  1591. DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
  1592. "mout_sclk_fsys_mmc1_sdclkin_b",
  1593. DIV_TOP_FSYS1, 0, 4),
  1594. DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
  1595. "dout_sclk_fsys_mmc1_sdclkin_a",
  1596. DIV_TOP_FSYS1, 4, 8),
  1597. DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
  1598. "mout_sclk_fsys_mmc2_sdclkin_b",
  1599. DIV_TOP_FSYS1, 12, 4),
  1600. DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
  1601. "dout_sclk_fsys_mmc2_sdclkin_a",
  1602. DIV_TOP_FSYS1, 16, 8),
  1603. };
  1604. static const struct samsung_gate_clock top_gate_clks[] __initconst = {
  1605. GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
  1606. "dout_sclk_fsys_mmc0_sdclkin_b",
  1607. EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
  1608. GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
  1609. "dout_sclk_fsys_mmc1_sdclkin_b",
  1610. EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
  1611. GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
  1612. "dout_sclk_fsys_mmc2_sdclkin_b",
  1613. EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
  1614. GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
  1615. EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
  1616. CLK_SET_RATE_PARENT, 0),
  1617. };
  1618. static const struct samsung_pll_clock top_pll_clks[] __initconst = {
  1619. PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
  1620. DISP_PLL_LOCK, DISP_PLL_CON0,
  1621. pll2550_24mhz_tbl),
  1622. PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
  1623. AUD_PLL_LOCK, AUD_PLL_CON0,
  1624. pll2650_24mhz_tbl),
  1625. };
  1626. static const struct samsung_cmu_info top_cmu __initconst = {
  1627. .pll_clks = top_pll_clks,
  1628. .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
  1629. .mux_clks = top_mux_clks,
  1630. .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
  1631. .div_clks = top_div_clks,
  1632. .nr_div_clks = ARRAY_SIZE(top_div_clks),
  1633. .gate_clks = top_gate_clks,
  1634. .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
  1635. .fixed_clks = fixed_rate_clks,
  1636. .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks),
  1637. .nr_clk_ids = TOP_NR_CLK,
  1638. .clk_regs = top_clk_regs,
  1639. .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
  1640. };
  1641. static void __init exynos5260_clk_top_init(struct device_node *np)
  1642. {
  1643. samsung_cmu_register_one(np, &top_cmu);
  1644. }
  1645. CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
  1646. exynos5260_clk_top_init);