clk-exynos5250.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. * Author: Thomas Abraham <thomas.ab@samsung.com>
  6. *
  7. * Common Clock Framework support for Exynos5250 SoC.
  8. */
  9. #include <dt-bindings/clock/exynos5250.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include "clk.h"
  15. #include "clk-cpu.h"
  16. #include "clk-exynos5-subcmu.h"
  17. #define APLL_LOCK 0x0
  18. #define APLL_CON0 0x100
  19. #define SRC_CPU 0x200
  20. #define DIV_CPU0 0x500
  21. #define PWR_CTRL1 0x1020
  22. #define PWR_CTRL2 0x1024
  23. #define MPLL_LOCK 0x4000
  24. #define MPLL_CON0 0x4100
  25. #define SRC_CORE1 0x4204
  26. #define GATE_IP_ACP 0x8800
  27. #define GATE_IP_ISP0 0xc800
  28. #define GATE_IP_ISP1 0xc804
  29. #define CPLL_LOCK 0x10020
  30. #define EPLL_LOCK 0x10030
  31. #define VPLL_LOCK 0x10040
  32. #define GPLL_LOCK 0x10050
  33. #define CPLL_CON0 0x10120
  34. #define EPLL_CON0 0x10130
  35. #define VPLL_CON0 0x10140
  36. #define GPLL_CON0 0x10150
  37. #define SRC_TOP0 0x10210
  38. #define SRC_TOP1 0x10214
  39. #define SRC_TOP2 0x10218
  40. #define SRC_TOP3 0x1021c
  41. #define SRC_GSCL 0x10220
  42. #define SRC_DISP1_0 0x1022c
  43. #define SRC_MAU 0x10240
  44. #define SRC_FSYS 0x10244
  45. #define SRC_GEN 0x10248
  46. #define SRC_PERIC0 0x10250
  47. #define SRC_PERIC1 0x10254
  48. #define SRC_MASK_GSCL 0x10320
  49. #define SRC_MASK_DISP1_0 0x1032c
  50. #define SRC_MASK_MAU 0x10334
  51. #define SRC_MASK_FSYS 0x10340
  52. #define SRC_MASK_GEN 0x10344
  53. #define SRC_MASK_PERIC0 0x10350
  54. #define SRC_MASK_PERIC1 0x10354
  55. #define DIV_TOP0 0x10510
  56. #define DIV_TOP1 0x10514
  57. #define DIV_GSCL 0x10520
  58. #define DIV_DISP1_0 0x1052c
  59. #define DIV_GEN 0x1053c
  60. #define DIV_MAU 0x10544
  61. #define DIV_FSYS0 0x10548
  62. #define DIV_FSYS1 0x1054c
  63. #define DIV_FSYS2 0x10550
  64. #define DIV_PERIC0 0x10558
  65. #define DIV_PERIC1 0x1055c
  66. #define DIV_PERIC2 0x10560
  67. #define DIV_PERIC3 0x10564
  68. #define DIV_PERIC4 0x10568
  69. #define DIV_PERIC5 0x1056c
  70. #define GATE_IP_GSCL 0x10920
  71. #define GATE_IP_DISP1 0x10928
  72. #define GATE_IP_MFC 0x1092c
  73. #define GATE_IP_G3D 0x10930
  74. #define GATE_IP_GEN 0x10934
  75. #define GATE_IP_FSYS 0x10944
  76. #define GATE_IP_PERIC 0x10950
  77. #define GATE_IP_PERIS 0x10960
  78. #define BPLL_LOCK 0x20010
  79. #define BPLL_CON0 0x20110
  80. #define SRC_CDREX 0x20200
  81. #define PLL_DIV2_SEL 0x20a24
  82. /*Below definitions are used for PWR_CTRL settings*/
  83. #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
  84. #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
  85. #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
  86. #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
  87. #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
  88. #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
  89. #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
  90. #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
  91. #define PWR_CTRL2_DIV2_UP_EN (1 << 25)
  92. #define PWR_CTRL2_DIV1_UP_EN (1 << 24)
  93. #define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
  94. #define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
  95. #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
  96. #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
  97. /* list of PLLs to be registered */
  98. enum exynos5250_plls {
  99. apll, mpll, cpll, epll, vpll, gpll, bpll,
  100. nr_plls /* number of PLLs */
  101. };
  102. static void __iomem *reg_base;
  103. /*
  104. * list of controller registers to be saved and restored during a
  105. * suspend/resume cycle.
  106. */
  107. static const unsigned long exynos5250_clk_regs[] __initconst = {
  108. SRC_CPU,
  109. DIV_CPU0,
  110. PWR_CTRL1,
  111. PWR_CTRL2,
  112. SRC_CORE1,
  113. SRC_TOP0,
  114. SRC_TOP1,
  115. SRC_TOP2,
  116. SRC_TOP3,
  117. SRC_GSCL,
  118. SRC_DISP1_0,
  119. SRC_MAU,
  120. SRC_FSYS,
  121. SRC_GEN,
  122. SRC_PERIC0,
  123. SRC_PERIC1,
  124. SRC_MASK_GSCL,
  125. SRC_MASK_DISP1_0,
  126. SRC_MASK_MAU,
  127. SRC_MASK_FSYS,
  128. SRC_MASK_GEN,
  129. SRC_MASK_PERIC0,
  130. SRC_MASK_PERIC1,
  131. DIV_TOP0,
  132. DIV_TOP1,
  133. DIV_GSCL,
  134. DIV_DISP1_0,
  135. DIV_GEN,
  136. DIV_MAU,
  137. DIV_FSYS0,
  138. DIV_FSYS1,
  139. DIV_FSYS2,
  140. DIV_PERIC0,
  141. DIV_PERIC1,
  142. DIV_PERIC2,
  143. DIV_PERIC3,
  144. DIV_PERIC4,
  145. DIV_PERIC5,
  146. GATE_IP_GSCL,
  147. GATE_IP_MFC,
  148. GATE_IP_G3D,
  149. GATE_IP_GEN,
  150. GATE_IP_FSYS,
  151. GATE_IP_PERIC,
  152. GATE_IP_PERIS,
  153. SRC_CDREX,
  154. PLL_DIV2_SEL,
  155. GATE_IP_DISP1,
  156. GATE_IP_ACP,
  157. GATE_IP_ISP0,
  158. GATE_IP_ISP1,
  159. };
  160. /* list of all parent clock list */
  161. PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
  162. PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
  163. PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
  164. PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
  165. PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
  166. PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
  167. PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
  168. PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
  169. PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
  170. PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
  171. PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
  172. PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
  173. PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
  174. PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
  175. PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
  176. PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid",
  177. "mout_aclk300_disp1_mid1" };
  178. PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
  179. PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
  180. PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
  181. PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
  182. PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
  183. PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
  184. PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
  185. PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
  186. PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
  187. PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
  188. "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
  189. "mout_mpll_user", "mout_epll", "mout_vpll",
  190. "mout_cpll", "none", "none",
  191. "none", "none", "none",
  192. "none" };
  193. PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
  194. "sclk_uhostphy", "fin_pll",
  195. "mout_mpll_user", "mout_epll", "mout_vpll",
  196. "mout_cpll", "none", "none",
  197. "none", "none", "none",
  198. "none" };
  199. PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
  200. "sclk_uhostphy", "fin_pll",
  201. "mout_mpll_user", "mout_epll", "mout_vpll",
  202. "mout_cpll", "none", "none",
  203. "none", "none", "none",
  204. "none" };
  205. PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
  206. "sclk_uhostphy", "fin_pll",
  207. "mout_mpll_user", "mout_epll", "mout_vpll",
  208. "mout_cpll", "none", "none",
  209. "none", "none", "none",
  210. "none" };
  211. PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
  212. "spdif_extclk" };
  213. /* fixed rate clocks generated outside the soc */
  214. static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
  215. FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
  216. };
  217. /* fixed rate clocks generated inside the soc */
  218. static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
  219. FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
  220. FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
  221. FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
  222. FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
  223. };
  224. static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
  225. FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
  226. FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
  227. };
  228. static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
  229. MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
  230. };
  231. static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
  232. /*
  233. * NOTE: Following table is sorted by (clock domain, register address,
  234. * bitfield shift) triplet in ascending order. When adding new entries,
  235. * please make sure that the order is kept, to avoid merge conflicts
  236. * and make further work with defined data easier.
  237. */
  238. /*
  239. * CMU_CPU
  240. */
  241. MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
  242. CLK_SET_RATE_PARENT, 0),
  243. MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
  244. /*
  245. * CMU_CORE
  246. */
  247. MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
  248. /*
  249. * CMU_TOP
  250. */
  251. MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
  252. MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
  253. MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
  254. MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
  255. MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
  256. MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
  257. MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
  258. 8, 1),
  259. MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
  260. MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
  261. MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
  262. MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
  263. MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
  264. MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
  265. MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
  266. MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
  267. MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
  268. mout_aclk200_sub_p, SRC_TOP3, 4, 1),
  269. MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
  270. mout_aclk300_sub_p, SRC_TOP3, 6, 1),
  271. MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
  272. MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
  273. MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
  274. SRC_TOP3, 20, 1),
  275. MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
  276. MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
  277. MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
  278. MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
  279. MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
  280. MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
  281. MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
  282. MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
  283. MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
  284. MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
  285. MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
  286. MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
  287. MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
  288. MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
  289. MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
  290. MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
  291. MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
  292. MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
  293. MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
  294. MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
  295. MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
  296. MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
  297. MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
  298. MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
  299. MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
  300. MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
  301. MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
  302. MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
  303. MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
  304. /*
  305. * CMU_CDREX
  306. */
  307. MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
  308. MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
  309. MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
  310. };
  311. static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
  312. /*
  313. * NOTE: Following table is sorted by (clock domain, register address,
  314. * bitfield shift) triplet in ascending order. When adding new entries,
  315. * please make sure that the order is kept, to avoid merge conflicts
  316. * and make further work with defined data easier.
  317. */
  318. /*
  319. * CMU_CPU
  320. */
  321. DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
  322. DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
  323. DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
  324. /*
  325. * CMU_TOP
  326. */
  327. DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
  328. DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
  329. DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
  330. DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
  331. DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
  332. DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
  333. 24, 3),
  334. DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
  335. DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
  336. DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
  337. DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
  338. DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
  339. DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
  340. DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
  341. DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
  342. DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
  343. DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
  344. DIV_F(0, "div_mipi1_pre", "div_mipi1",
  345. DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
  346. DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
  347. DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
  348. DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
  349. DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
  350. DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
  351. DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
  352. DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
  353. DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
  354. DIV_F(0, "div_mmc_pre0", "div_mmc0",
  355. DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
  356. DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
  357. DIV_F(0, "div_mmc_pre1", "div_mmc1",
  358. DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
  359. DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
  360. DIV_F(0, "div_mmc_pre2", "div_mmc2",
  361. DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
  362. DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
  363. DIV_F(0, "div_mmc_pre3", "div_mmc3",
  364. DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
  365. DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
  366. DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
  367. DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
  368. DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
  369. DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
  370. DIV_F(0, "div_spi_pre0", "div_spi0",
  371. DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
  372. DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
  373. DIV_F(0, "div_spi_pre1", "div_spi1",
  374. DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
  375. DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
  376. DIV_F(0, "div_spi_pre2", "div_spi2",
  377. DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
  378. DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
  379. DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
  380. DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
  381. DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
  382. DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
  383. DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
  384. DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
  385. };
  386. static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
  387. /*
  388. * NOTE: Following table is sorted by (clock domain, register address,
  389. * bitfield shift) triplet in ascending order. When adding new entries,
  390. * please make sure that the order is kept, to avoid merge conflicts
  391. * and make further work with defined data easier.
  392. */
  393. /*
  394. * CMU_ACP
  395. */
  396. GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
  397. GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
  398. GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
  399. GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
  400. /*
  401. * CMU_TOP
  402. */
  403. GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
  404. SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
  405. GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
  406. SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
  407. GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
  408. SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
  409. GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
  410. SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
  411. GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
  412. SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
  413. GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
  414. SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
  415. GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
  416. SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
  417. GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
  418. SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
  419. GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
  420. SRC_MASK_DISP1_0, 20, 0, 0),
  421. GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
  422. SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
  423. GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
  424. SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
  425. GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
  426. SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
  427. GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
  428. SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
  429. GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
  430. SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
  431. GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
  432. SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
  433. GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
  434. SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
  435. GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
  436. SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
  437. GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
  438. SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
  439. GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
  440. SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
  441. GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
  442. SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
  443. GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
  444. SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
  445. GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
  446. SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
  447. GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
  448. SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
  449. GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
  450. SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
  451. GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
  452. SRC_MASK_PERIC1, 4, 0, 0),
  453. GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
  454. SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
  455. GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
  456. SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
  457. GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
  458. SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
  459. GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
  460. 0),
  461. GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
  462. 0),
  463. GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
  464. 0),
  465. GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
  466. 0),
  467. GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub",
  468. GATE_IP_GSCL, 4, 0, 0),
  469. GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
  470. GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
  471. GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
  472. GATE_IP_GSCL, 7, 0, 0),
  473. GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
  474. GATE_IP_GSCL, 8, 0, 0),
  475. GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
  476. GATE_IP_GSCL, 9, 0, 0),
  477. GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
  478. GATE_IP_GSCL, 10, 0, 0),
  479. GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub",
  480. GATE_IP_GSCL, 11, 0, 0),
  481. GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub",
  482. GATE_IP_GSCL, 12, 0, 0),
  483. GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
  484. GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
  485. 0),
  486. GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
  487. 0),
  488. GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
  489. CLK_SET_RATE_PARENT, 0),
  490. GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
  491. GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
  492. GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
  493. GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
  494. 0),
  495. GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
  496. GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
  497. GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
  498. GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
  499. GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
  500. GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
  501. GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
  502. GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
  503. GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
  504. GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
  505. GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
  506. GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
  507. GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
  508. GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
  509. GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
  510. GATE_IP_FSYS, 24, 0, 0),
  511. GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
  512. 0),
  513. GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
  514. GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
  515. GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
  516. GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
  517. GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
  518. GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
  519. GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
  520. GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
  521. GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
  522. GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
  523. GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
  524. GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
  525. GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
  526. GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
  527. GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
  528. GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
  529. GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
  530. GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
  531. GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
  532. GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
  533. GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
  534. GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
  535. GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
  536. GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
  537. GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
  538. GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
  539. GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
  540. GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
  541. GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
  542. GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
  543. GATE(CLK_SYSREG, "sysreg", "div_aclk66",
  544. GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
  545. GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
  546. 0),
  547. GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
  548. GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
  549. GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
  550. GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
  551. GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
  552. GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
  553. GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
  554. GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
  555. GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
  556. GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
  557. GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
  558. GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
  559. GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
  560. GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
  561. GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
  562. GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
  563. GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
  564. GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
  565. GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
  566. GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
  567. GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
  568. GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
  569. GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
  570. GATE_IP_ISP0, 8, 0, 0),
  571. GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
  572. GATE_IP_ISP0, 9, 0, 0),
  573. GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
  574. GATE_IP_ISP0, 10, 0, 0),
  575. GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
  576. GATE_IP_ISP0, 11, 0, 0),
  577. GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
  578. GATE_IP_ISP0, 12, 0, 0),
  579. GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
  580. GATE_IP_ISP0, 13, 0, 0),
  581. GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
  582. GATE_IP_ISP1, 4, 0, 0),
  583. GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
  584. GATE_IP_ISP1, 5, 0, 0),
  585. GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
  586. GATE_IP_ISP1, 6, 0, 0),
  587. GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
  588. GATE_IP_ISP1, 7, 0, 0),
  589. };
  590. static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {
  591. GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
  592. 0),
  593. GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
  594. 0),
  595. GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
  596. 0),
  597. GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
  598. GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
  599. 0),
  600. GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
  601. 0),
  602. GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
  603. GATE_IP_DISP1, 9, 0, 0),
  604. GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
  605. GATE_IP_DISP1, 8, 0, 0),
  606. };
  607. static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {
  608. { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
  609. { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */
  610. { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */
  611. };
  612. static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
  613. .gate_clks = exynos5250_disp_gate_clks,
  614. .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks),
  615. .suspend_regs = exynos5250_disp_suspend_regs,
  616. .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs),
  617. .pd_name = "DISP1",
  618. };
  619. static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
  620. &exynos5250_disp_subcmu,
  621. };
  622. static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
  623. /* sorted in descending order */
  624. /* PLL_36XX_RATE(rate, m, p, s, k) */
  625. PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
  626. /* Not in UM, but need for eDP on snow */
  627. PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
  628. { },
  629. };
  630. static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
  631. /* sorted in descending order */
  632. /* PLL_36XX_RATE(rate, m, p, s, k) */
  633. PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
  634. PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
  635. PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
  636. PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
  637. PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
  638. PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
  639. PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
  640. PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
  641. { },
  642. };
  643. static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
  644. /* sorted in descending order */
  645. /* PLL_35XX_RATE(fin, rate, m, p, s) */
  646. PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
  647. PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
  648. PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
  649. PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
  650. PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
  651. PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
  652. PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
  653. PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
  654. PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
  655. PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
  656. PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
  657. PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
  658. PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
  659. PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
  660. PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
  661. PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
  662. };
  663. static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
  664. [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
  665. APLL_CON0, NULL),
  666. [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
  667. MPLL_CON0, NULL),
  668. [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
  669. BPLL_CON0, NULL),
  670. [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
  671. GPLL_CON0, NULL),
  672. [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
  673. CPLL_CON0, NULL),
  674. [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
  675. EPLL_CON0, NULL),
  676. [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
  677. VPLL_LOCK, VPLL_CON0, NULL),
  678. };
  679. #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
  680. ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
  681. ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
  682. #define E5250_CPU_DIV1(hpm, copy) \
  683. (((hpm) << 4) | (copy))
  684. static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
  685. { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
  686. { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
  687. { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
  688. { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
  689. { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
  690. { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
  691. { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
  692. { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  693. { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  694. { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  695. { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  696. { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  697. { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  698. { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  699. { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  700. { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
  701. { 0 },
  702. };
  703. static const struct of_device_id ext_clk_match[] __initconst = {
  704. { .compatible = "samsung,clock-xxti", .data = (void *)0, },
  705. { },
  706. };
  707. /* register exynox5250 clocks */
  708. static void __init exynos5250_clk_init(struct device_node *np)
  709. {
  710. struct samsung_clk_provider *ctx;
  711. unsigned int tmp;
  712. struct clk_hw **hws;
  713. if (np) {
  714. reg_base = of_iomap(np, 0);
  715. if (!reg_base)
  716. panic("%s: failed to map registers\n", __func__);
  717. } else {
  718. panic("%s: unable to determine soc\n", __func__);
  719. }
  720. ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
  721. hws = ctx->clk_data.hws;
  722. samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
  723. ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
  724. ext_clk_match);
  725. samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
  726. ARRAY_SIZE(exynos5250_pll_pmux_clks));
  727. if (_get_rate("fin_pll") == 24 * MHZ) {
  728. exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
  729. exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
  730. }
  731. if (_get_rate("mout_vpllsrc") == 24 * MHZ)
  732. exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
  733. samsung_clk_register_pll(ctx, exynos5250_plls,
  734. ARRAY_SIZE(exynos5250_plls),
  735. reg_base);
  736. samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
  737. ARRAY_SIZE(exynos5250_fixed_rate_clks));
  738. samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
  739. ARRAY_SIZE(exynos5250_fixed_factor_clks));
  740. samsung_clk_register_mux(ctx, exynos5250_mux_clks,
  741. ARRAY_SIZE(exynos5250_mux_clks));
  742. samsung_clk_register_div(ctx, exynos5250_div_clks,
  743. ARRAY_SIZE(exynos5250_div_clks));
  744. samsung_clk_register_gate(ctx, exynos5250_gate_clks,
  745. ARRAY_SIZE(exynos5250_gate_clks));
  746. exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
  747. hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
  748. exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
  749. CLK_CPU_HAS_DIV1);
  750. /*
  751. * Enable arm clock down (in idle) and set arm divider
  752. * ratios in WFI/WFE state.
  753. */
  754. tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
  755. PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
  756. PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
  757. PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
  758. __raw_writel(tmp, reg_base + PWR_CTRL1);
  759. /*
  760. * Enable arm clock up (on exiting idle). Set arm divider
  761. * ratios when not in idle along with the standby duration
  762. * ratios.
  763. */
  764. tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
  765. PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
  766. PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
  767. __raw_writel(tmp, reg_base + PWR_CTRL2);
  768. samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
  769. ARRAY_SIZE(exynos5250_clk_regs));
  770. exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
  771. exynos5250_subcmus);
  772. samsung_clk_of_add_provider(np, ctx);
  773. pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
  774. _get_rate("div_arm2"));
  775. }
  776. CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);