clk-exynos5-subcmu.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 Samsung Electronics Co., Ltd.
  4. // Author: Marek Szyprowski <m.szyprowski@samsung.com>
  5. // Common Clock Framework support for Exynos5 power-domain dependent clocks
  6. #include <linux/io.h>
  7. #include <linux/of_platform.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pm_domain.h>
  10. #include <linux/pm_runtime.h>
  11. #include "clk.h"
  12. #include "clk-exynos5-subcmu.h"
  13. static struct samsung_clk_provider *ctx;
  14. static const struct exynos5_subcmu_info **cmu;
  15. static int nr_cmus;
  16. static void exynos5_subcmu_clk_save(void __iomem *base,
  17. struct exynos5_subcmu_reg_dump *rd,
  18. unsigned int num_regs)
  19. {
  20. for (; num_regs > 0; --num_regs, ++rd) {
  21. rd->save = readl(base + rd->offset);
  22. writel((rd->save & ~rd->mask) | rd->value, base + rd->offset);
  23. rd->save &= rd->mask;
  24. }
  25. };
  26. static void exynos5_subcmu_clk_restore(void __iomem *base,
  27. struct exynos5_subcmu_reg_dump *rd,
  28. unsigned int num_regs)
  29. {
  30. for (; num_regs > 0; --num_regs, ++rd)
  31. writel((readl(base + rd->offset) & ~rd->mask) | rd->save,
  32. base + rd->offset);
  33. }
  34. static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx,
  35. const struct samsung_gate_clock *list, int nr_clk)
  36. {
  37. while (nr_clk--)
  38. samsung_clk_add_lookup(ctx, ERR_PTR(-EPROBE_DEFER), list++->id);
  39. }
  40. /*
  41. * Pass the needed clock provider context and register sub-CMU clocks
  42. *
  43. * NOTE: This function has to be called from the main, OF_CLK_DECLARE-
  44. * initialized clock provider driver. This happens very early during boot
  45. * process. Then this driver, during core_initcall registers two platform
  46. * drivers: one which binds to the same device-tree node as OF_CLK_DECLARE
  47. * driver and second, for handling its per-domain child-devices. Those
  48. * platform drivers are bound to their devices a bit later in arch_initcall,
  49. * when OF-core populates all device-tree nodes.
  50. */
  51. void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus,
  52. const struct exynos5_subcmu_info **_cmu)
  53. {
  54. ctx = _ctx;
  55. cmu = _cmu;
  56. nr_cmus = _nr_cmus;
  57. for (; _nr_cmus--; _cmu++) {
  58. exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
  59. (*_cmu)->nr_gate_clks);
  60. exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
  61. (*_cmu)->nr_suspend_regs);
  62. }
  63. }
  64. static int __maybe_unused exynos5_subcmu_suspend(struct device *dev)
  65. {
  66. struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
  67. unsigned long flags;
  68. spin_lock_irqsave(&ctx->lock, flags);
  69. exynos5_subcmu_clk_save(ctx->reg_base, info->suspend_regs,
  70. info->nr_suspend_regs);
  71. spin_unlock_irqrestore(&ctx->lock, flags);
  72. return 0;
  73. }
  74. static int __maybe_unused exynos5_subcmu_resume(struct device *dev)
  75. {
  76. struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
  77. unsigned long flags;
  78. spin_lock_irqsave(&ctx->lock, flags);
  79. exynos5_subcmu_clk_restore(ctx->reg_base, info->suspend_regs,
  80. info->nr_suspend_regs);
  81. spin_unlock_irqrestore(&ctx->lock, flags);
  82. return 0;
  83. }
  84. static int __init exynos5_subcmu_probe(struct platform_device *pdev)
  85. {
  86. struct device *dev = &pdev->dev;
  87. struct exynos5_subcmu_info *info = dev_get_drvdata(dev);
  88. pm_runtime_set_suspended(dev);
  89. pm_runtime_enable(dev);
  90. pm_runtime_get(dev);
  91. ctx->dev = dev;
  92. samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks);
  93. samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks);
  94. ctx->dev = NULL;
  95. pm_runtime_put_sync(dev);
  96. return 0;
  97. }
  98. static const struct dev_pm_ops exynos5_subcmu_pm_ops = {
  99. SET_RUNTIME_PM_OPS(exynos5_subcmu_suspend,
  100. exynos5_subcmu_resume, NULL)
  101. SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  102. pm_runtime_force_resume)
  103. };
  104. static struct platform_driver exynos5_subcmu_driver __refdata = {
  105. .driver = {
  106. .name = "exynos5-subcmu",
  107. .suppress_bind_attrs = true,
  108. .pm = &exynos5_subcmu_pm_ops,
  109. },
  110. .probe = exynos5_subcmu_probe,
  111. };
  112. static int __init exynos5_clk_register_subcmu(struct device *parent,
  113. const struct exynos5_subcmu_info *info,
  114. struct device_node *pd_node)
  115. {
  116. struct of_phandle_args genpdspec = { .np = pd_node };
  117. struct platform_device *pdev;
  118. int ret;
  119. pdev = platform_device_alloc("exynos5-subcmu", PLATFORM_DEVID_AUTO);
  120. if (!pdev)
  121. return -ENOMEM;
  122. pdev->dev.parent = parent;
  123. platform_set_drvdata(pdev, (void *)info);
  124. of_genpd_add_device(&genpdspec, &pdev->dev);
  125. ret = platform_device_add(pdev);
  126. if (ret)
  127. platform_device_put(pdev);
  128. return ret;
  129. }
  130. static int __init exynos5_clk_probe(struct platform_device *pdev)
  131. {
  132. struct device_node *np;
  133. const char *name;
  134. int i;
  135. for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
  136. if (of_property_read_string(np, "label", &name) < 0)
  137. continue;
  138. for (i = 0; i < nr_cmus; i++)
  139. if (strcmp(cmu[i]->pd_name, name) == 0)
  140. exynos5_clk_register_subcmu(&pdev->dev,
  141. cmu[i], np);
  142. }
  143. return 0;
  144. }
  145. static const struct of_device_id exynos5_clk_of_match[] = {
  146. { .compatible = "samsung,exynos5250-clock", },
  147. { .compatible = "samsung,exynos5420-clock", },
  148. { .compatible = "samsung,exynos5800-clock", },
  149. { },
  150. };
  151. static struct platform_driver exynos5_clk_driver __refdata = {
  152. .driver = {
  153. .name = "exynos5-clock",
  154. .of_match_table = exynos5_clk_of_match,
  155. .suppress_bind_attrs = true,
  156. },
  157. .probe = exynos5_clk_probe,
  158. };
  159. static int __init exynos5_clk_drv_init(void)
  160. {
  161. platform_driver_register(&exynos5_clk_driver);
  162. platform_driver_register(&exynos5_subcmu_driver);
  163. return 0;
  164. }
  165. core_initcall(exynos5_clk_drv_init);