clk-exynos4.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. * Author: Thomas Abraham <thomas.ab@samsung.com>
  6. *
  7. * Common Clock Framework support for all Exynos4 SoCs.
  8. */
  9. #include <dt-bindings/clock/exynos4.h>
  10. #include <linux/slab.h>
  11. #include <linux/clk.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include "clk.h"
  17. #include "clk-cpu.h"
  18. /* Exynos4 clock controller register offsets */
  19. #define SRC_LEFTBUS 0x4200
  20. #define DIV_LEFTBUS 0x4500
  21. #define GATE_IP_LEFTBUS 0x4800
  22. #define E4X12_GATE_IP_IMAGE 0x4930
  23. #define CLKOUT_CMU_LEFTBUS 0x4a00
  24. #define SRC_RIGHTBUS 0x8200
  25. #define DIV_RIGHTBUS 0x8500
  26. #define GATE_IP_RIGHTBUS 0x8800
  27. #define E4X12_GATE_IP_PERIR 0x8960
  28. #define CLKOUT_CMU_RIGHTBUS 0x8a00
  29. #define EPLL_LOCK 0xc010
  30. #define VPLL_LOCK 0xc020
  31. #define EPLL_CON0 0xc110
  32. #define EPLL_CON1 0xc114
  33. #define EPLL_CON2 0xc118
  34. #define VPLL_CON0 0xc120
  35. #define VPLL_CON1 0xc124
  36. #define VPLL_CON2 0xc128
  37. #define SRC_TOP0 0xc210
  38. #define SRC_TOP1 0xc214
  39. #define SRC_CAM 0xc220
  40. #define SRC_TV 0xc224
  41. #define SRC_MFC 0xc228
  42. #define SRC_G3D 0xc22c
  43. #define E4210_SRC_IMAGE 0xc230
  44. #define SRC_LCD0 0xc234
  45. #define E4210_SRC_LCD1 0xc238
  46. #define E4X12_SRC_ISP 0xc238
  47. #define SRC_MAUDIO 0xc23c
  48. #define SRC_FSYS 0xc240
  49. #define SRC_PERIL0 0xc250
  50. #define SRC_PERIL1 0xc254
  51. #define E4X12_SRC_CAM1 0xc258
  52. #define SRC_MASK_TOP 0xc310
  53. #define SRC_MASK_CAM 0xc320
  54. #define SRC_MASK_TV 0xc324
  55. #define SRC_MASK_LCD0 0xc334
  56. #define E4210_SRC_MASK_LCD1 0xc338
  57. #define E4X12_SRC_MASK_ISP 0xc338
  58. #define SRC_MASK_MAUDIO 0xc33c
  59. #define SRC_MASK_FSYS 0xc340
  60. #define SRC_MASK_PERIL0 0xc350
  61. #define SRC_MASK_PERIL1 0xc354
  62. #define DIV_TOP 0xc510
  63. #define DIV_CAM 0xc520
  64. #define DIV_TV 0xc524
  65. #define DIV_MFC 0xc528
  66. #define DIV_G3D 0xc52c
  67. #define DIV_IMAGE 0xc530
  68. #define DIV_LCD0 0xc534
  69. #define E4210_DIV_LCD1 0xc538
  70. #define E4X12_DIV_ISP 0xc538
  71. #define DIV_MAUDIO 0xc53c
  72. #define DIV_FSYS0 0xc540
  73. #define DIV_FSYS1 0xc544
  74. #define DIV_FSYS2 0xc548
  75. #define DIV_FSYS3 0xc54c
  76. #define DIV_PERIL0 0xc550
  77. #define DIV_PERIL1 0xc554
  78. #define DIV_PERIL2 0xc558
  79. #define DIV_PERIL3 0xc55c
  80. #define DIV_PERIL4 0xc560
  81. #define DIV_PERIL5 0xc564
  82. #define E4X12_DIV_CAM1 0xc568
  83. #define E4X12_GATE_BUS_FSYS1 0xc744
  84. #define GATE_SCLK_CAM 0xc820
  85. #define GATE_IP_CAM 0xc920
  86. #define GATE_IP_TV 0xc924
  87. #define GATE_IP_MFC 0xc928
  88. #define GATE_IP_G3D 0xc92c
  89. #define E4210_GATE_IP_IMAGE 0xc930
  90. #define GATE_IP_LCD0 0xc934
  91. #define E4210_GATE_IP_LCD1 0xc938
  92. #define E4X12_GATE_IP_ISP 0xc938
  93. #define E4X12_GATE_IP_MAUDIO 0xc93c
  94. #define GATE_IP_FSYS 0xc940
  95. #define GATE_IP_GPS 0xc94c
  96. #define GATE_IP_PERIL 0xc950
  97. #define E4210_GATE_IP_PERIR 0xc960
  98. #define GATE_BLOCK 0xc970
  99. #define CLKOUT_CMU_TOP 0xca00
  100. #define E4X12_MPLL_LOCK 0x10008
  101. #define E4X12_MPLL_CON0 0x10108
  102. #define SRC_DMC 0x10200
  103. #define SRC_MASK_DMC 0x10300
  104. #define DIV_DMC0 0x10500
  105. #define DIV_DMC1 0x10504
  106. #define GATE_IP_DMC 0x10900
  107. #define CLKOUT_CMU_DMC 0x10a00
  108. #define APLL_LOCK 0x14000
  109. #define E4210_MPLL_LOCK 0x14008
  110. #define APLL_CON0 0x14100
  111. #define E4210_MPLL_CON0 0x14108
  112. #define SRC_CPU 0x14200
  113. #define DIV_CPU0 0x14500
  114. #define DIV_CPU1 0x14504
  115. #define GATE_SCLK_CPU 0x14800
  116. #define GATE_IP_CPU 0x14900
  117. #define CLKOUT_CMU_CPU 0x14a00
  118. #define PWR_CTRL1 0x15020
  119. #define E4X12_PWR_CTRL2 0x15024
  120. /* Below definitions are used for PWR_CTRL settings */
  121. #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
  122. #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
  123. #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
  124. #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
  125. #define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
  126. #define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
  127. #define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
  128. #define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
  129. #define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
  130. #define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
  131. #define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
  132. #define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
  133. /* the exynos4 soc type */
  134. enum exynos4_soc {
  135. EXYNOS4210,
  136. EXYNOS4X12,
  137. };
  138. /* list of PLLs to be registered */
  139. enum exynos4_plls {
  140. apll, mpll, epll, vpll,
  141. nr_plls /* number of PLLs */
  142. };
  143. static void __iomem *reg_base;
  144. static enum exynos4_soc exynos4_soc;
  145. /*
  146. * list of controller registers to be saved and restored during a
  147. * suspend/resume cycle.
  148. */
  149. static const unsigned long exynos4210_clk_save[] __initconst = {
  150. E4210_SRC_IMAGE,
  151. E4210_SRC_LCD1,
  152. E4210_SRC_MASK_LCD1,
  153. E4210_DIV_LCD1,
  154. E4210_GATE_IP_IMAGE,
  155. E4210_GATE_IP_LCD1,
  156. E4210_GATE_IP_PERIR,
  157. E4210_MPLL_CON0,
  158. PWR_CTRL1,
  159. };
  160. static const unsigned long exynos4x12_clk_save[] __initconst = {
  161. E4X12_GATE_IP_IMAGE,
  162. E4X12_GATE_IP_PERIR,
  163. E4X12_SRC_CAM1,
  164. E4X12_DIV_ISP,
  165. E4X12_DIV_CAM1,
  166. E4X12_MPLL_CON0,
  167. PWR_CTRL1,
  168. E4X12_PWR_CTRL2,
  169. };
  170. static const unsigned long exynos4_clk_regs[] __initconst = {
  171. EPLL_LOCK,
  172. VPLL_LOCK,
  173. EPLL_CON0,
  174. EPLL_CON1,
  175. EPLL_CON2,
  176. VPLL_CON0,
  177. VPLL_CON1,
  178. VPLL_CON2,
  179. SRC_LEFTBUS,
  180. DIV_LEFTBUS,
  181. GATE_IP_LEFTBUS,
  182. SRC_RIGHTBUS,
  183. DIV_RIGHTBUS,
  184. GATE_IP_RIGHTBUS,
  185. SRC_TOP0,
  186. SRC_TOP1,
  187. SRC_CAM,
  188. SRC_TV,
  189. SRC_MFC,
  190. SRC_G3D,
  191. SRC_LCD0,
  192. SRC_MAUDIO,
  193. SRC_FSYS,
  194. SRC_PERIL0,
  195. SRC_PERIL1,
  196. SRC_MASK_TOP,
  197. SRC_MASK_CAM,
  198. SRC_MASK_TV,
  199. SRC_MASK_LCD0,
  200. SRC_MASK_MAUDIO,
  201. SRC_MASK_FSYS,
  202. SRC_MASK_PERIL0,
  203. SRC_MASK_PERIL1,
  204. DIV_TOP,
  205. DIV_CAM,
  206. DIV_TV,
  207. DIV_MFC,
  208. DIV_G3D,
  209. DIV_IMAGE,
  210. DIV_LCD0,
  211. DIV_MAUDIO,
  212. DIV_FSYS0,
  213. DIV_FSYS1,
  214. DIV_FSYS2,
  215. DIV_FSYS3,
  216. DIV_PERIL0,
  217. DIV_PERIL1,
  218. DIV_PERIL2,
  219. DIV_PERIL3,
  220. DIV_PERIL4,
  221. DIV_PERIL5,
  222. GATE_SCLK_CAM,
  223. GATE_IP_CAM,
  224. GATE_IP_TV,
  225. GATE_IP_MFC,
  226. GATE_IP_G3D,
  227. GATE_IP_LCD0,
  228. GATE_IP_FSYS,
  229. GATE_IP_GPS,
  230. GATE_IP_PERIL,
  231. GATE_BLOCK,
  232. SRC_MASK_DMC,
  233. SRC_DMC,
  234. DIV_DMC0,
  235. DIV_DMC1,
  236. GATE_IP_DMC,
  237. APLL_CON0,
  238. SRC_CPU,
  239. DIV_CPU0,
  240. DIV_CPU1,
  241. GATE_SCLK_CPU,
  242. GATE_IP_CPU,
  243. CLKOUT_CMU_LEFTBUS,
  244. CLKOUT_CMU_RIGHTBUS,
  245. CLKOUT_CMU_TOP,
  246. CLKOUT_CMU_DMC,
  247. CLKOUT_CMU_CPU,
  248. };
  249. static const struct samsung_clk_reg_dump src_mask_suspend[] = {
  250. { .offset = VPLL_CON0, .value = 0x80600302, },
  251. { .offset = EPLL_CON0, .value = 0x806F0302, },
  252. { .offset = SRC_MASK_TOP, .value = 0x00000001, },
  253. { .offset = SRC_MASK_CAM, .value = 0x11111111, },
  254. { .offset = SRC_MASK_TV, .value = 0x00000111, },
  255. { .offset = SRC_MASK_LCD0, .value = 0x00001111, },
  256. { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, },
  257. { .offset = SRC_MASK_FSYS, .value = 0x01011111, },
  258. { .offset = SRC_MASK_PERIL0, .value = 0x01111111, },
  259. { .offset = SRC_MASK_PERIL1, .value = 0x01110111, },
  260. { .offset = SRC_MASK_DMC, .value = 0x00010000, },
  261. };
  262. static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
  263. { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, },
  264. };
  265. /* list of all parent clock list */
  266. PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
  267. PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
  268. PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
  269. PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
  270. PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
  271. PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
  272. PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
  273. PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
  274. PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
  275. PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
  276. PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
  277. PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
  278. "spdif_extclk", };
  279. PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
  280. PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
  281. /* Exynos 4210-specific parent groups */
  282. PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
  283. PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
  284. PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
  285. PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
  286. "sclk_usbphy0", "none", "sclk_hdmiphy",
  287. "sclk_mpll", "sclk_epll", "sclk_vpll", };
  288. PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
  289. "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
  290. "sclk_epll", "sclk_vpll" };
  291. PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
  292. "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
  293. "sclk_epll", "sclk_vpll", };
  294. PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
  295. "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
  296. "sclk_epll", "sclk_vpll", };
  297. PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
  298. PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
  299. PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
  300. "sclk_usbphy1", "sclk_hdmiphy", "none",
  301. "sclk_epll", "sclk_vpll" };
  302. PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
  303. "div_gdl", "div_gpl" };
  304. PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
  305. "div_gdr", "div_gpr" };
  306. PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
  307. "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
  308. "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
  309. "aclk160", "aclk133", "aclk200", "aclk100",
  310. "sclk_mfc", "sclk_g3d", "sclk_g2d",
  311. "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
  312. "s_rxbyteclkhs0_4l" };
  313. PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
  314. "div_dphy", "none", "div_pwi" };
  315. PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
  316. "none", "arm_clk_div_2", "div_corem0",
  317. "div_corem1", "div_corem0", "div_atb",
  318. "div_periph", "div_pclk_dbg", "div_hpm" };
  319. /* Exynos 4x12-specific parent groups */
  320. PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
  321. PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
  322. PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
  323. PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
  324. PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
  325. PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
  326. "none", "sclk_hdmiphy", "mout_mpll_user_t",
  327. "sclk_epll", "sclk_vpll", };
  328. PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
  329. "sclk_usbphy0", "xxti", "xusbxti",
  330. "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
  331. PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
  332. "sclk_usbphy0", "xxti", "xusbxti",
  333. "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
  334. PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
  335. "sclk_usbphy0", "xxti", "xusbxti",
  336. "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
  337. PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
  338. PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
  339. PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
  340. PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
  341. PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
  342. "none", "sclk_hdmiphy", "sclk_mpll",
  343. "sclk_epll", "sclk_vpll" };
  344. PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
  345. "div_gdl", "div_gpl" };
  346. PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
  347. "div_gdr", "div_gpr" };
  348. PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
  349. "sclk_usbphy0", "none", "sclk_hdmiphy",
  350. "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
  351. "aclk160", "aclk133", "aclk200", "aclk100",
  352. "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
  353. "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
  354. "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
  355. "rx_half_byte_clk_csis1", "div_jpeg",
  356. "sclk_pwm_isp", "sclk_spi0_isp",
  357. "sclk_spi1_isp", "sclk_uart_isp",
  358. "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
  359. "sclk_pcm0" };
  360. PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
  361. "div_dmc", "div_dphy", "fout_mpll_div_2",
  362. "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
  363. PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
  364. "arm_clk_div_2", "div_corem0", "div_corem1",
  365. "div_cores", "div_atb", "div_periph",
  366. "div_pclk_dbg", "div_hpm" };
  367. /* fixed rate clocks generated outside the soc */
  368. static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
  369. FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
  370. FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
  371. };
  372. /* fixed rate clocks generated inside the soc */
  373. static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
  374. FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
  375. FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
  376. FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
  377. };
  378. static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
  379. FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
  380. };
  381. static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
  382. FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
  383. FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
  384. FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
  385. FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
  386. };
  387. static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
  388. FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
  389. };
  390. static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
  391. FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
  392. FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
  393. FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
  394. FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
  395. };
  396. /* list of mux clocks supported in all exynos4 soc's */
  397. static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
  398. MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
  399. CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
  400. MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
  401. MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
  402. MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
  403. MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
  404. CLK_SET_RATE_PARENT, 0),
  405. MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
  406. CLK_SET_RATE_PARENT, 0),
  407. MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
  408. MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
  409. MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
  410. MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
  411. MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
  412. MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
  413. };
  414. /* list of mux clocks supported in exynos4210 soc */
  415. static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
  416. MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
  417. };
  418. static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
  419. MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
  420. MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
  421. CLKOUT_CMU_LEFTBUS, 0, 5),
  422. MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
  423. MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
  424. CLKOUT_CMU_RIGHTBUS, 0, 5),
  425. MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
  426. MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
  427. MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
  428. MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
  429. MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
  430. MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
  431. MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
  432. MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
  433. MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
  434. MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
  435. MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
  436. MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
  437. MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
  438. MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
  439. MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
  440. MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
  441. MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
  442. MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
  443. MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
  444. MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
  445. MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
  446. MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
  447. MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
  448. MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
  449. MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
  450. CLK_SET_RATE_PARENT, 0),
  451. MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
  452. MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
  453. MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
  454. MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
  455. MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
  456. MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
  457. MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
  458. MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
  459. MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
  460. MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
  461. MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
  462. MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
  463. MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
  464. MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
  465. MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
  466. MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
  467. MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
  468. MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
  469. MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
  470. MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
  471. MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
  472. MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
  473. MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
  474. };
  475. /* list of mux clocks supported in exynos4x12 soc */
  476. static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
  477. MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
  478. MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
  479. MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
  480. CLKOUT_CMU_LEFTBUS, 0, 5),
  481. MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
  482. MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
  483. MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
  484. CLKOUT_CMU_RIGHTBUS, 0, 5),
  485. MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
  486. SRC_CPU, 24, 1),
  487. MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
  488. MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
  489. MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
  490. MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
  491. SRC_TOP1, 12, 1),
  492. MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
  493. SRC_TOP1, 16, 1),
  494. MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
  495. MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
  496. mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
  497. MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
  498. MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
  499. MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
  500. MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
  501. MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
  502. MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
  503. MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
  504. MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
  505. MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
  506. MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
  507. MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
  508. MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
  509. MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
  510. MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
  511. MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
  512. MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
  513. MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
  514. MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
  515. MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
  516. MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
  517. MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
  518. MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
  519. MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
  520. MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
  521. CLK_SET_RATE_PARENT, 0),
  522. MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
  523. MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
  524. MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
  525. MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
  526. MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
  527. MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
  528. MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
  529. MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
  530. MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
  531. MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
  532. MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
  533. MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
  534. MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
  535. MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
  536. MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
  537. MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
  538. MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
  539. MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
  540. MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
  541. MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
  542. MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
  543. MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
  544. MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
  545. MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
  546. MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
  547. MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
  548. MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
  549. MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
  550. MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
  551. MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
  552. };
  553. /* list of divider clocks supported in all exynos4 soc's */
  554. static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
  555. DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
  556. DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
  557. DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
  558. CLKOUT_CMU_LEFTBUS, 8, 6),
  559. DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
  560. DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
  561. DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
  562. CLKOUT_CMU_RIGHTBUS, 8, 6),
  563. DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
  564. DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
  565. DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
  566. DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
  567. DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
  568. DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
  569. DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
  570. DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
  571. DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
  572. DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
  573. DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
  574. DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
  575. DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
  576. DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
  577. DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
  578. DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
  579. DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
  580. DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
  581. DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
  582. DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
  583. DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
  584. DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
  585. DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
  586. DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
  587. DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
  588. DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
  589. DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
  590. DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
  591. DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
  592. DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
  593. DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
  594. DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
  595. DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
  596. DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
  597. DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
  598. DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
  599. DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
  600. DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
  601. DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
  602. DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
  603. CLK_SET_RATE_PARENT, 0),
  604. DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
  605. DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
  606. DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
  607. DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
  608. DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
  609. DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
  610. DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
  611. DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
  612. DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
  613. DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
  614. DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
  615. DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
  616. DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
  617. DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
  618. DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
  619. CLK_SET_RATE_PARENT, 0),
  620. DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
  621. CLK_SET_RATE_PARENT, 0),
  622. DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
  623. CLK_SET_RATE_PARENT, 0),
  624. DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
  625. CLK_SET_RATE_PARENT, 0),
  626. DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
  627. CLK_SET_RATE_PARENT, 0),
  628. DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
  629. DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
  630. DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
  631. DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
  632. DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
  633. DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
  634. DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
  635. DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
  636. DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
  637. };
  638. /* list of divider clocks supported in exynos4210 soc */
  639. static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
  640. DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
  641. DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
  642. DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
  643. DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
  644. DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
  645. DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
  646. CLK_SET_RATE_PARENT, 0),
  647. };
  648. /* list of divider clocks supported in exynos4x12 soc */
  649. static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
  650. DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
  651. DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
  652. DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
  653. DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
  654. DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
  655. DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
  656. DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
  657. DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
  658. DIV_TOP, 24, 3),
  659. DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
  660. DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
  661. DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
  662. DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
  663. DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
  664. DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
  665. DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
  666. DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
  667. DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
  668. };
  669. /* list of gate clocks supported in all exynos4 soc's */
  670. static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
  671. GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
  672. GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
  673. GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
  674. GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
  675. 0),
  676. GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
  677. GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
  678. GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
  679. GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
  680. GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
  681. GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
  682. GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
  683. 0),
  684. GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
  685. GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
  686. GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
  687. GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
  688. GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
  689. GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
  690. GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
  691. GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
  692. GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
  693. GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
  694. GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
  695. GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
  696. CLK_SET_RATE_PARENT, 0),
  697. GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
  698. CLK_SET_RATE_PARENT, 0),
  699. GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
  700. SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
  701. GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
  702. CLK_SET_RATE_PARENT, 0),
  703. GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
  704. CLK_SET_RATE_PARENT, 0),
  705. GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
  706. GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
  707. GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
  708. GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
  709. GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
  710. GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
  711. GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
  712. CLK_SET_RATE_PARENT, 0),
  713. GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
  714. CLK_SET_RATE_PARENT, 0),
  715. GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
  716. CLK_SET_RATE_PARENT, 0),
  717. GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
  718. CLK_SET_RATE_PARENT, 0),
  719. GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
  720. CLK_SET_RATE_PARENT, 0),
  721. GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
  722. CLK_SET_RATE_PARENT, 0),
  723. GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
  724. CLK_SET_RATE_PARENT, 0),
  725. GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
  726. CLK_SET_RATE_PARENT, 0),
  727. GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
  728. CLK_SET_RATE_PARENT, 0),
  729. GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
  730. CLK_SET_RATE_PARENT, 0),
  731. GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
  732. CLK_SET_RATE_PARENT, 0),
  733. GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
  734. CLK_SET_RATE_PARENT, 0),
  735. GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
  736. CLK_SET_RATE_PARENT, 0),
  737. GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
  738. CLK_SET_RATE_PARENT, 0),
  739. GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
  740. CLK_SET_RATE_PARENT, 0),
  741. GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
  742. CLK_SET_RATE_PARENT, 0),
  743. GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
  744. CLK_SET_RATE_PARENT, 0),
  745. GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
  746. CLK_SET_RATE_PARENT, 0),
  747. GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
  748. CLK_SET_RATE_PARENT, 0),
  749. GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
  750. CLK_SET_RATE_PARENT, 0),
  751. GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
  752. CLK_SET_RATE_PARENT, 0),
  753. GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
  754. 0, 0),
  755. GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
  756. 0, 0),
  757. GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
  758. 0, 0),
  759. GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
  760. 0, 0),
  761. GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
  762. 0, 0),
  763. GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
  764. 0, 0),
  765. GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
  766. 0, 0),
  767. GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
  768. 0, 0),
  769. GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
  770. 0, 0),
  771. GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
  772. 0, 0),
  773. GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
  774. 0, 0),
  775. GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
  776. GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
  777. GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
  778. GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
  779. 0, 0),
  780. GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
  781. GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
  782. GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
  783. 0, 0),
  784. GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
  785. 0, 0),
  786. GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
  787. GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
  788. GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
  789. 0, 0),
  790. GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
  791. 0, 0),
  792. GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
  793. GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
  794. 0, 0),
  795. GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
  796. 0, 0),
  797. GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
  798. 0, 0),
  799. GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
  800. 0, 0),
  801. GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
  802. 0, 0),
  803. GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
  804. 0, 0),
  805. GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
  806. GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
  807. 0, 0),
  808. GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
  809. 0, 0),
  810. GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
  811. 0, 0),
  812. GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
  813. 0, 0),
  814. GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
  815. 0, 0),
  816. GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
  817. 0, 0),
  818. GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
  819. 0, 0),
  820. GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
  821. 0, 0),
  822. GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
  823. 0, 0),
  824. GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
  825. 0, 0),
  826. GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
  827. 0, 0),
  828. GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
  829. 0, 0),
  830. GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
  831. 0, 0),
  832. GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
  833. 0, 0),
  834. GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
  835. 0, 0),
  836. GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
  837. 0, 0),
  838. GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
  839. 0, 0),
  840. GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
  841. 0, 0),
  842. GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
  843. 0, 0),
  844. GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
  845. 0, 0),
  846. GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
  847. 0, 0),
  848. GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
  849. 0, 0),
  850. GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
  851. 0, 0),
  852. GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
  853. GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
  854. GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
  855. GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
  856. GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
  857. GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
  858. CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
  859. GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
  860. CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
  861. GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
  862. CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
  863. GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
  864. CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
  865. GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
  866. CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
  867. };
  868. /* list of gate clocks supported in exynos4210 soc */
  869. static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
  870. GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
  871. GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
  872. GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
  873. GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
  874. GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
  875. GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
  876. 0),
  877. GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
  878. 0),
  879. GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
  880. GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
  881. GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
  882. GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
  883. GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
  884. GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
  885. GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
  886. GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
  887. GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
  888. CLK_IGNORE_UNUSED, 0),
  889. GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
  890. 0),
  891. GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
  892. E4210_GATE_IP_IMAGE, 4, 0, 0),
  893. GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
  894. E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
  895. GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
  896. SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
  897. GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
  898. GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
  899. GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
  900. 0, 0),
  901. GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
  902. 0, 0),
  903. GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
  904. 0, 0),
  905. GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
  906. 0, 0),
  907. GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
  908. 0, 0),
  909. GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
  910. CLK_SET_RATE_PARENT, 0),
  911. GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
  912. 0),
  913. };
  914. /* list of gate clocks supported in exynos4x12 soc */
  915. static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
  916. GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),
  917. GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
  918. GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
  919. GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
  920. GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
  921. GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
  922. 0),
  923. GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
  924. 0),
  925. GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
  926. GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
  927. GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
  928. GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
  929. CLK_IGNORE_UNUSED, 0),
  930. GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
  931. 0),
  932. GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
  933. SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
  934. GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
  935. SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
  936. GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
  937. SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
  938. GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
  939. E4X12_GATE_IP_IMAGE, 4, 0, 0),
  940. GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
  941. 0, 0),
  942. GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
  943. 0, 0),
  944. GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
  945. GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
  946. E4X12_GATE_IP_ISP, 0, 0, 0),
  947. GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
  948. E4X12_GATE_IP_ISP, 1, 0, 0),
  949. GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
  950. E4X12_GATE_IP_ISP, 2, 0, 0),
  951. GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
  952. E4X12_GATE_IP_ISP, 3, 0, 0),
  953. GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
  954. GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
  955. 0, 0),
  956. GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
  957. 0, 0),
  958. GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
  959. GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
  960. GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
  961. 0),
  962. };
  963. /*
  964. * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
  965. * resides in chipid register space, outside of the clock controller memory
  966. * mapped space. So to determine the parent of fin_pll clock, the chipid
  967. * controller is first remapped and the value of XOM[0] bit is read to
  968. * determine the parent clock.
  969. */
  970. static unsigned long __init exynos4_get_xom(void)
  971. {
  972. unsigned long xom = 0;
  973. void __iomem *chipid_base;
  974. struct device_node *np;
  975. np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
  976. if (np) {
  977. chipid_base = of_iomap(np, 0);
  978. if (chipid_base)
  979. xom = readl(chipid_base + 8);
  980. iounmap(chipid_base);
  981. of_node_put(np);
  982. }
  983. return xom;
  984. }
  985. static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
  986. {
  987. struct samsung_fixed_rate_clock fclk;
  988. struct clk *clk;
  989. unsigned long finpll_f = 24000000;
  990. char *parent_name;
  991. unsigned int xom = exynos4_get_xom();
  992. parent_name = xom & 1 ? "xusbxti" : "xxti";
  993. clk = clk_get(NULL, parent_name);
  994. if (IS_ERR(clk)) {
  995. pr_err("%s: failed to lookup parent clock %s, assuming "
  996. "fin_pll clock frequency is 24MHz\n", __func__,
  997. parent_name);
  998. } else {
  999. finpll_f = clk_get_rate(clk);
  1000. }
  1001. fclk.id = CLK_FIN_PLL;
  1002. fclk.name = "fin_pll";
  1003. fclk.parent_name = NULL;
  1004. fclk.flags = 0;
  1005. fclk.fixed_rate = finpll_f;
  1006. samsung_clk_register_fixed_rate(ctx, &fclk, 1);
  1007. }
  1008. static const struct of_device_id ext_clk_match[] __initconst = {
  1009. { .compatible = "samsung,clock-xxti", .data = (void *)0, },
  1010. { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
  1011. {},
  1012. };
  1013. /* PLLs PMS values */
  1014. static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
  1015. PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
  1016. PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
  1017. PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
  1018. PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
  1019. PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
  1020. PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
  1021. PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
  1022. PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
  1023. PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
  1024. { /* sentinel */ }
  1025. };
  1026. static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
  1027. PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
  1028. PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
  1029. PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1, 0, 0),
  1030. PLL_4600_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710, 1),
  1031. PLL_4600_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762, 1),
  1032. PLL_4600_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961, 0),
  1033. PLL_4600_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381, 0),
  1034. { /* sentinel */ }
  1035. };
  1036. static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
  1037. PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
  1038. PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1, 1, 1),
  1039. PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
  1040. PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
  1041. PLL_4650_RATE(24 * MHZ, 55360351, 53, 3, 3, 2417, 0, 17, 0),
  1042. { /* sentinel */ }
  1043. };
  1044. static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
  1045. PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
  1046. PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
  1047. PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
  1048. PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
  1049. PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
  1050. PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
  1051. PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
  1052. PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
  1053. PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
  1054. PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
  1055. PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
  1056. PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
  1057. PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
  1058. PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
  1059. PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
  1060. PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
  1061. { /* sentinel */ }
  1062. };
  1063. static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
  1064. PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
  1065. PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
  1066. PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
  1067. PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),
  1068. PLL_36XX_RATE(24 * MHZ, 73727996, 73, 3, 3, 47710),
  1069. PLL_36XX_RATE(24 * MHZ, 67737602, 90, 4, 3, 20762),
  1070. PLL_36XX_RATE(24 * MHZ, 49151992, 49, 3, 3, 9961),
  1071. PLL_36XX_RATE(24 * MHZ, 45158401, 45, 3, 3, 10381),
  1072. { /* sentinel */ }
  1073. };
  1074. static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
  1075. PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
  1076. PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1, 0),
  1077. PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2, 0),
  1078. PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2, 0),
  1079. PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),
  1080. PLL_36XX_RATE(24 * MHZ, 106031250, 53, 3, 2, 1024),
  1081. PLL_36XX_RATE(24 * MHZ, 53015625, 53, 3, 3, 1024),
  1082. { /* sentinel */ }
  1083. };
  1084. static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
  1085. [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
  1086. APLL_LOCK, APLL_CON0, NULL),
  1087. [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
  1088. E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
  1089. [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
  1090. EPLL_LOCK, EPLL_CON0, NULL),
  1091. [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
  1092. VPLL_LOCK, VPLL_CON0, NULL),
  1093. };
  1094. static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
  1095. [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
  1096. APLL_LOCK, APLL_CON0, NULL),
  1097. [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
  1098. E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
  1099. [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
  1100. EPLL_LOCK, EPLL_CON0, NULL),
  1101. [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
  1102. VPLL_LOCK, VPLL_CON0, NULL),
  1103. };
  1104. static void __init exynos4x12_core_down_clock(void)
  1105. {
  1106. unsigned int tmp;
  1107. /*
  1108. * Enable arm clock down (in idle) and set arm divider
  1109. * ratios in WFI/WFE state.
  1110. */
  1111. tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
  1112. PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
  1113. PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
  1114. PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
  1115. /* On Exynos4412 enable it also on core 2 and 3 */
  1116. if (num_possible_cpus() == 4)
  1117. tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
  1118. PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
  1119. writel_relaxed(tmp, reg_base + PWR_CTRL1);
  1120. /*
  1121. * Disable the clock up feature in case it was enabled by bootloader.
  1122. */
  1123. writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
  1124. }
  1125. #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
  1126. (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
  1127. ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4))
  1128. #define E4210_CPU_DIV1(hpm, copy) \
  1129. (((hpm) << 4) | ((copy) << 0))
  1130. static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
  1131. { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
  1132. { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
  1133. { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
  1134. { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
  1135. { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
  1136. { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
  1137. { 0 },
  1138. };
  1139. #define E4412_CPU_DIV1(cores, hpm, copy) \
  1140. (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
  1141. static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
  1142. { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
  1143. { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
  1144. { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
  1145. { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
  1146. { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
  1147. { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
  1148. { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
  1149. { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
  1150. { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
  1151. { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
  1152. { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
  1153. { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
  1154. { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
  1155. { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
  1156. { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
  1157. { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
  1158. { 0 },
  1159. };
  1160. /* register exynos4 clocks */
  1161. static void __init exynos4_clk_init(struct device_node *np,
  1162. enum exynos4_soc soc)
  1163. {
  1164. struct samsung_clk_provider *ctx;
  1165. struct clk_hw **hws;
  1166. exynos4_soc = soc;
  1167. reg_base = of_iomap(np, 0);
  1168. if (!reg_base)
  1169. panic("%s: failed to map registers\n", __func__);
  1170. ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
  1171. hws = ctx->clk_data.hws;
  1172. samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
  1173. ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
  1174. ext_clk_match);
  1175. exynos4_clk_register_finpll(ctx);
  1176. if (exynos4_soc == EXYNOS4210) {
  1177. samsung_clk_register_mux(ctx, exynos4210_mux_early,
  1178. ARRAY_SIZE(exynos4210_mux_early));
  1179. if (_get_rate("fin_pll") == 24000000) {
  1180. exynos4210_plls[apll].rate_table =
  1181. exynos4210_apll_rates;
  1182. exynos4210_plls[epll].rate_table =
  1183. exynos4210_epll_rates;
  1184. }
  1185. if (_get_rate("mout_vpllsrc") == 24000000)
  1186. exynos4210_plls[vpll].rate_table =
  1187. exynos4210_vpll_rates;
  1188. samsung_clk_register_pll(ctx, exynos4210_plls,
  1189. ARRAY_SIZE(exynos4210_plls), reg_base);
  1190. } else {
  1191. if (_get_rate("fin_pll") == 24000000) {
  1192. exynos4x12_plls[apll].rate_table =
  1193. exynos4x12_apll_rates;
  1194. exynos4x12_plls[epll].rate_table =
  1195. exynos4x12_epll_rates;
  1196. exynos4x12_plls[vpll].rate_table =
  1197. exynos4x12_vpll_rates;
  1198. }
  1199. samsung_clk_register_pll(ctx, exynos4x12_plls,
  1200. ARRAY_SIZE(exynos4x12_plls), reg_base);
  1201. }
  1202. samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
  1203. ARRAY_SIZE(exynos4_fixed_rate_clks));
  1204. samsung_clk_register_mux(ctx, exynos4_mux_clks,
  1205. ARRAY_SIZE(exynos4_mux_clks));
  1206. samsung_clk_register_div(ctx, exynos4_div_clks,
  1207. ARRAY_SIZE(exynos4_div_clks));
  1208. samsung_clk_register_gate(ctx, exynos4_gate_clks,
  1209. ARRAY_SIZE(exynos4_gate_clks));
  1210. samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
  1211. ARRAY_SIZE(exynos4_fixed_factor_clks));
  1212. if (exynos4_soc == EXYNOS4210) {
  1213. samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
  1214. ARRAY_SIZE(exynos4210_fixed_rate_clks));
  1215. samsung_clk_register_mux(ctx, exynos4210_mux_clks,
  1216. ARRAY_SIZE(exynos4210_mux_clks));
  1217. samsung_clk_register_div(ctx, exynos4210_div_clks,
  1218. ARRAY_SIZE(exynos4210_div_clks));
  1219. samsung_clk_register_gate(ctx, exynos4210_gate_clks,
  1220. ARRAY_SIZE(exynos4210_gate_clks));
  1221. samsung_clk_register_fixed_factor(ctx,
  1222. exynos4210_fixed_factor_clks,
  1223. ARRAY_SIZE(exynos4210_fixed_factor_clks));
  1224. exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
  1225. hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
  1226. e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
  1227. CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
  1228. } else {
  1229. samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
  1230. ARRAY_SIZE(exynos4x12_mux_clks));
  1231. samsung_clk_register_div(ctx, exynos4x12_div_clks,
  1232. ARRAY_SIZE(exynos4x12_div_clks));
  1233. samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
  1234. ARRAY_SIZE(exynos4x12_gate_clks));
  1235. samsung_clk_register_fixed_factor(ctx,
  1236. exynos4x12_fixed_factor_clks,
  1237. ARRAY_SIZE(exynos4x12_fixed_factor_clks));
  1238. exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
  1239. hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
  1240. e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
  1241. CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
  1242. }
  1243. if (soc == EXYNOS4X12)
  1244. exynos4x12_core_down_clock();
  1245. samsung_clk_extended_sleep_init(reg_base,
  1246. exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
  1247. src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
  1248. if (exynos4_soc == EXYNOS4210)
  1249. samsung_clk_extended_sleep_init(reg_base,
  1250. exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
  1251. src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
  1252. else
  1253. samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
  1254. ARRAY_SIZE(exynos4x12_clk_save));
  1255. samsung_clk_of_add_provider(np, ctx);
  1256. pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
  1257. "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
  1258. exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
  1259. _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
  1260. _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
  1261. _get_rate("div_core2"));
  1262. }
  1263. static void __init exynos4210_clk_init(struct device_node *np)
  1264. {
  1265. exynos4_clk_init(np, EXYNOS4210);
  1266. }
  1267. CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
  1268. static void __init exynos4412_clk_init(struct device_node *np)
  1269. {
  1270. exynos4_clk_init(np, EXYNOS4X12);
  1271. }
  1272. CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);