clk-cpu.h 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  4. *
  5. * Common Clock Framework support for all PLL's in Samsung platforms
  6. */
  7. #ifndef __SAMSUNG_CLK_CPU_H
  8. #define __SAMSUNG_CLK_CPU_H
  9. #include "clk.h"
  10. /**
  11. * struct exynos_cpuclk_data: config data to setup cpu clocks.
  12. * @prate: frequency of the primary parent clock (in KHz).
  13. * @div0: value to be programmed in the div_cpu0 register.
  14. * @div1: value to be programmed in the div_cpu1 register.
  15. *
  16. * This structure holds the divider configuration data for dividers in the CPU
  17. * clock domain. The parent frequency at which these divider values are valid is
  18. * specified in @prate. The @prate is the frequency of the primary parent clock.
  19. * For CPU clock domains that do not have a DIV1 register, the @div1 member
  20. * value is not used.
  21. */
  22. struct exynos_cpuclk_cfg_data {
  23. unsigned long prate;
  24. unsigned long div0;
  25. unsigned long div1;
  26. };
  27. /**
  28. * struct exynos_cpuclk: information about clock supplied to a CPU core.
  29. * @hw: handle between CCF and CPU clock.
  30. * @alt_parent: alternate parent clock to use when switching the speed
  31. * of the primary parent clock.
  32. * @ctrl_base: base address of the clock controller.
  33. * @lock: cpu clock domain register access lock.
  34. * @cfg: cpu clock rate configuration data.
  35. * @num_cfgs: number of array elements in @cfg array.
  36. * @clk_nb: clock notifier registered for changes in clock speed of the
  37. * primary parent clock.
  38. * @flags: configuration flags for the CPU clock.
  39. *
  40. * This structure holds information required for programming the CPU clock for
  41. * various clock speeds.
  42. */
  43. struct exynos_cpuclk {
  44. struct clk_hw hw;
  45. const struct clk_hw *alt_parent;
  46. void __iomem *ctrl_base;
  47. spinlock_t *lock;
  48. const struct exynos_cpuclk_cfg_data *cfg;
  49. const unsigned long num_cfgs;
  50. struct notifier_block clk_nb;
  51. unsigned long flags;
  52. /* The CPU clock registers have DIV1 configuration register */
  53. #define CLK_CPU_HAS_DIV1 (1 << 0)
  54. /* When ALT parent is active, debug clocks need safe divider values */
  55. #define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
  56. /* The CPU clock registers have Exynos5433-compatible layout */
  57. #define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
  58. };
  59. int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
  60. unsigned int lookup_id, const char *name,
  61. const struct clk_hw *parent, const struct clk_hw *alt_parent,
  62. unsigned long offset,
  63. const struct exynos_cpuclk_cfg_data *cfg,
  64. unsigned long num_cfgs, unsigned long flags);
  65. #endif /* __SAMSUNG_CLK_CPU_H */