clk-cpu.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  4. * Author: Thomas Abraham <thomas.ab@samsung.com>
  5. *
  6. * Copyright (c) 2015 Samsung Electronics Co., Ltd.
  7. * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
  8. *
  9. * This file contains the utility function to register CPU clock for Samsung
  10. * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
  11. * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
  12. * blocks which includes mux and divider blocks. There are a number of other
  13. * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
  14. * clock for CPU domain. The rates of these auxiliary clocks are related to the
  15. * CPU clock rate and this relation is usually specified in the hardware manual
  16. * of the SoC or supplied after the SoC characterization.
  17. *
  18. * The below implementation of the CPU clock allows the rate changes of the CPU
  19. * clock and the corresponding rate changes of the auxillary clocks of the CPU
  20. * domain. The platform clock driver provides a clock register configuration
  21. * for each configurable rate which is then used to program the clock hardware
  22. * registers to acheive a fast co-oridinated rate change for all the CPU domain
  23. * clocks.
  24. *
  25. * On a rate change request for the CPU clock, the rate change is propagated
  26. * upto the PLL supplying the clock to the CPU domain clock blocks. While the
  27. * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
  28. * alternate clock source. If required, the alternate clock source is divided
  29. * down in order to keep the output clock rate within the previous OPP limits.
  30. */
  31. #include <linux/errno.h>
  32. #include <linux/io.h>
  33. #include <linux/slab.h>
  34. #include <linux/clk.h>
  35. #include <linux/clk-provider.h>
  36. #include "clk-cpu.h"
  37. #define E4210_SRC_CPU 0x0
  38. #define E4210_STAT_CPU 0x200
  39. #define E4210_DIV_CPU0 0x300
  40. #define E4210_DIV_CPU1 0x304
  41. #define E4210_DIV_STAT_CPU0 0x400
  42. #define E4210_DIV_STAT_CPU1 0x404
  43. #define E5433_MUX_SEL2 0x008
  44. #define E5433_MUX_STAT2 0x208
  45. #define E5433_DIV_CPU0 0x400
  46. #define E5433_DIV_CPU1 0x404
  47. #define E5433_DIV_STAT_CPU0 0x500
  48. #define E5433_DIV_STAT_CPU1 0x504
  49. #define E4210_DIV0_RATIO0_MASK 0x7
  50. #define E4210_DIV1_HPM_MASK (0x7 << 4)
  51. #define E4210_DIV1_COPY_MASK (0x7 << 0)
  52. #define E4210_MUX_HPM_MASK (1 << 20)
  53. #define E4210_DIV0_ATB_SHIFT 16
  54. #define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
  55. #define MAX_DIV 8
  56. #define DIV_MASK 7
  57. #define DIV_MASK_ALL 0xffffffff
  58. #define MUX_MASK 7
  59. /*
  60. * Helper function to wait until divider(s) have stabilized after the divider
  61. * value has changed.
  62. */
  63. static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
  64. {
  65. unsigned long timeout = jiffies + msecs_to_jiffies(10);
  66. do {
  67. if (!(readl(div_reg) & mask))
  68. return;
  69. } while (time_before(jiffies, timeout));
  70. if (!(readl(div_reg) & mask))
  71. return;
  72. pr_err("%s: timeout in divider stablization\n", __func__);
  73. }
  74. /*
  75. * Helper function to wait until mux has stabilized after the mux selection
  76. * value was changed.
  77. */
  78. static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
  79. unsigned long mux_value)
  80. {
  81. unsigned long timeout = jiffies + msecs_to_jiffies(10);
  82. do {
  83. if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
  84. return;
  85. } while (time_before(jiffies, timeout));
  86. if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
  87. return;
  88. pr_err("%s: re-parenting mux timed-out\n", __func__);
  89. }
  90. /* common round rate callback useable for all types of CPU clocks */
  91. static long exynos_cpuclk_round_rate(struct clk_hw *hw,
  92. unsigned long drate, unsigned long *prate)
  93. {
  94. struct clk_hw *parent = clk_hw_get_parent(hw);
  95. *prate = clk_hw_round_rate(parent, drate);
  96. return *prate;
  97. }
  98. /* common recalc rate callback useable for all types of CPU clocks */
  99. static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
  100. unsigned long parent_rate)
  101. {
  102. /*
  103. * The CPU clock output (armclk) rate is the same as its parent
  104. * rate. Although there exist certain dividers inside the CPU
  105. * clock block that could be used to divide the parent clock,
  106. * the driver does not make use of them currently, except during
  107. * frequency transitions.
  108. */
  109. return parent_rate;
  110. }
  111. static const struct clk_ops exynos_cpuclk_clk_ops = {
  112. .recalc_rate = exynos_cpuclk_recalc_rate,
  113. .round_rate = exynos_cpuclk_round_rate,
  114. };
  115. /*
  116. * Helper function to set the 'safe' dividers for the CPU clock. The parameters
  117. * div and mask contain the divider value and the register bit mask of the
  118. * dividers to be programmed.
  119. */
  120. static void exynos_set_safe_div(void __iomem *base, unsigned long div,
  121. unsigned long mask)
  122. {
  123. unsigned long div0;
  124. div0 = readl(base + E4210_DIV_CPU0);
  125. div0 = (div0 & ~mask) | (div & mask);
  126. writel(div0, base + E4210_DIV_CPU0);
  127. wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
  128. }
  129. /* handler for pre-rate change notification from parent clock */
  130. static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
  131. struct exynos_cpuclk *cpuclk, void __iomem *base)
  132. {
  133. const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
  134. unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
  135. unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
  136. unsigned long div0, div1 = 0, mux_reg;
  137. unsigned long flags;
  138. /* find out the divider values to use for clock data */
  139. while ((cfg_data->prate * 1000) != ndata->new_rate) {
  140. if (cfg_data->prate == 0)
  141. return -EINVAL;
  142. cfg_data++;
  143. }
  144. spin_lock_irqsave(cpuclk->lock, flags);
  145. /*
  146. * For the selected PLL clock frequency, get the pre-defined divider
  147. * values. If the clock for sclk_hpm is not sourced from apll, then
  148. * the values for DIV_COPY and DIV_HPM dividers need not be set.
  149. */
  150. div0 = cfg_data->div0;
  151. if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
  152. div1 = cfg_data->div1;
  153. if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
  154. div1 = readl(base + E4210_DIV_CPU1) &
  155. (E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
  156. }
  157. /*
  158. * If the old parent clock speed is less than the clock speed of
  159. * the alternate parent, then it should be ensured that at no point
  160. * the armclk speed is more than the old_prate until the dividers are
  161. * set. Also workaround the issue of the dividers being set to lower
  162. * values before the parent clock speed is set to new lower speed
  163. * (this can result in too high speed of armclk output clocks).
  164. */
  165. if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
  166. unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
  167. alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
  168. WARN_ON(alt_div >= MAX_DIV);
  169. if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
  170. /*
  171. * In Exynos4210, ATB clock parent is also mout_core. So
  172. * ATB clock also needs to be mantained at safe speed.
  173. */
  174. alt_div |= E4210_DIV0_ATB_MASK;
  175. alt_div_mask |= E4210_DIV0_ATB_MASK;
  176. }
  177. exynos_set_safe_div(base, alt_div, alt_div_mask);
  178. div0 |= alt_div;
  179. }
  180. /* select sclk_mpll as the alternate parent */
  181. mux_reg = readl(base + E4210_SRC_CPU);
  182. writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);
  183. wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2);
  184. /* alternate parent is active now. set the dividers */
  185. writel(div0, base + E4210_DIV_CPU0);
  186. wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
  187. if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
  188. writel(div1, base + E4210_DIV_CPU1);
  189. wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
  190. DIV_MASK_ALL);
  191. }
  192. spin_unlock_irqrestore(cpuclk->lock, flags);
  193. return 0;
  194. }
  195. /* handler for post-rate change notification from parent clock */
  196. static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
  197. struct exynos_cpuclk *cpuclk, void __iomem *base)
  198. {
  199. const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
  200. unsigned long div = 0, div_mask = DIV_MASK;
  201. unsigned long mux_reg;
  202. unsigned long flags;
  203. /* find out the divider values to use for clock data */
  204. if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
  205. while ((cfg_data->prate * 1000) != ndata->new_rate) {
  206. if (cfg_data->prate == 0)
  207. return -EINVAL;
  208. cfg_data++;
  209. }
  210. }
  211. spin_lock_irqsave(cpuclk->lock, flags);
  212. /* select mout_apll as the alternate parent */
  213. mux_reg = readl(base + E4210_SRC_CPU);
  214. writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
  215. wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
  216. if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
  217. div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
  218. div_mask |= E4210_DIV0_ATB_MASK;
  219. }
  220. exynos_set_safe_div(base, div, div_mask);
  221. spin_unlock_irqrestore(cpuclk->lock, flags);
  222. return 0;
  223. }
  224. /*
  225. * Helper function to set the 'safe' dividers for the CPU clock. The parameters
  226. * div and mask contain the divider value and the register bit mask of the
  227. * dividers to be programmed.
  228. */
  229. static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
  230. unsigned long mask)
  231. {
  232. unsigned long div0;
  233. div0 = readl(base + E5433_DIV_CPU0);
  234. div0 = (div0 & ~mask) | (div & mask);
  235. writel(div0, base + E5433_DIV_CPU0);
  236. wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);
  237. }
  238. /* handler for pre-rate change notification from parent clock */
  239. static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
  240. struct exynos_cpuclk *cpuclk, void __iomem *base)
  241. {
  242. const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
  243. unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
  244. unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
  245. unsigned long div0, div1 = 0, mux_reg;
  246. unsigned long flags;
  247. /* find out the divider values to use for clock data */
  248. while ((cfg_data->prate * 1000) != ndata->new_rate) {
  249. if (cfg_data->prate == 0)
  250. return -EINVAL;
  251. cfg_data++;
  252. }
  253. spin_lock_irqsave(cpuclk->lock, flags);
  254. /*
  255. * For the selected PLL clock frequency, get the pre-defined divider
  256. * values.
  257. */
  258. div0 = cfg_data->div0;
  259. div1 = cfg_data->div1;
  260. /*
  261. * If the old parent clock speed is less than the clock speed of
  262. * the alternate parent, then it should be ensured that at no point
  263. * the armclk speed is more than the old_prate until the dividers are
  264. * set. Also workaround the issue of the dividers being set to lower
  265. * values before the parent clock speed is set to new lower speed
  266. * (this can result in too high speed of armclk output clocks).
  267. */
  268. if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
  269. unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
  270. alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
  271. WARN_ON(alt_div >= MAX_DIV);
  272. exynos5433_set_safe_div(base, alt_div, alt_div_mask);
  273. div0 |= alt_div;
  274. }
  275. /* select the alternate parent */
  276. mux_reg = readl(base + E5433_MUX_SEL2);
  277. writel(mux_reg | 1, base + E5433_MUX_SEL2);
  278. wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);
  279. /* alternate parent is active now. set the dividers */
  280. writel(div0, base + E5433_DIV_CPU0);
  281. wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);
  282. writel(div1, base + E5433_DIV_CPU1);
  283. wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);
  284. spin_unlock_irqrestore(cpuclk->lock, flags);
  285. return 0;
  286. }
  287. /* handler for post-rate change notification from parent clock */
  288. static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
  289. struct exynos_cpuclk *cpuclk, void __iomem *base)
  290. {
  291. unsigned long div = 0, div_mask = DIV_MASK;
  292. unsigned long mux_reg;
  293. unsigned long flags;
  294. spin_lock_irqsave(cpuclk->lock, flags);
  295. /* select apll as the alternate parent */
  296. mux_reg = readl(base + E5433_MUX_SEL2);
  297. writel(mux_reg & ~1, base + E5433_MUX_SEL2);
  298. wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);
  299. exynos5433_set_safe_div(base, div, div_mask);
  300. spin_unlock_irqrestore(cpuclk->lock, flags);
  301. return 0;
  302. }
  303. /*
  304. * This notifier function is called for the pre-rate and post-rate change
  305. * notifications of the parent clock of cpuclk.
  306. */
  307. static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
  308. unsigned long event, void *data)
  309. {
  310. struct clk_notifier_data *ndata = data;
  311. struct exynos_cpuclk *cpuclk;
  312. void __iomem *base;
  313. int err = 0;
  314. cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
  315. base = cpuclk->ctrl_base;
  316. if (event == PRE_RATE_CHANGE)
  317. err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
  318. else if (event == POST_RATE_CHANGE)
  319. err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
  320. return notifier_from_errno(err);
  321. }
  322. /*
  323. * This notifier function is called for the pre-rate and post-rate change
  324. * notifications of the parent clock of cpuclk.
  325. */
  326. static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
  327. unsigned long event, void *data)
  328. {
  329. struct clk_notifier_data *ndata = data;
  330. struct exynos_cpuclk *cpuclk;
  331. void __iomem *base;
  332. int err = 0;
  333. cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
  334. base = cpuclk->ctrl_base;
  335. if (event == PRE_RATE_CHANGE)
  336. err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
  337. else if (event == POST_RATE_CHANGE)
  338. err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
  339. return notifier_from_errno(err);
  340. }
  341. /* helper function to register a CPU clock */
  342. int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
  343. unsigned int lookup_id, const char *name,
  344. const struct clk_hw *parent, const struct clk_hw *alt_parent,
  345. unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
  346. unsigned long num_cfgs, unsigned long flags)
  347. {
  348. struct exynos_cpuclk *cpuclk;
  349. struct clk_init_data init;
  350. const char *parent_name;
  351. int ret = 0;
  352. if (IS_ERR(parent) || IS_ERR(alt_parent)) {
  353. pr_err("%s: invalid parent clock(s)\n", __func__);
  354. return -EINVAL;
  355. }
  356. cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
  357. if (!cpuclk)
  358. return -ENOMEM;
  359. parent_name = clk_hw_get_name(parent);
  360. init.name = name;
  361. init.flags = CLK_SET_RATE_PARENT;
  362. init.parent_names = &parent_name;
  363. init.num_parents = 1;
  364. init.ops = &exynos_cpuclk_clk_ops;
  365. cpuclk->alt_parent = alt_parent;
  366. cpuclk->hw.init = &init;
  367. cpuclk->ctrl_base = ctx->reg_base + offset;
  368. cpuclk->lock = &ctx->lock;
  369. cpuclk->flags = flags;
  370. if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
  371. cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
  372. else
  373. cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
  374. ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
  375. if (ret) {
  376. pr_err("%s: failed to register clock notifier for %s\n",
  377. __func__, name);
  378. goto free_cpuclk;
  379. }
  380. cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
  381. if (!cpuclk->cfg) {
  382. ret = -ENOMEM;
  383. goto unregister_clk_nb;
  384. }
  385. ret = clk_hw_register(NULL, &cpuclk->hw);
  386. if (ret) {
  387. pr_err("%s: could not register cpuclk %s\n", __func__, name);
  388. goto free_cpuclk_data;
  389. }
  390. samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);
  391. return 0;
  392. free_cpuclk_data:
  393. kfree(cpuclk->cfg);
  394. unregister_clk_nb:
  395. clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);
  396. free_cpuclk:
  397. kfree(cpuclk);
  398. return ret;
  399. }