kirkwood.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Kirkwood SoC clocks
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  9. * Andrew Lunn <andrew@lunn.ch>
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/slab.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include "common.h"
  19. /*
  20. * Core Clocks
  21. *
  22. * Kirkwood PLL sample-at-reset configuration
  23. * (6180 has different SAR layout than other Kirkwood SoCs)
  24. *
  25. * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
  26. * 4 = 600 MHz
  27. * 6 = 800 MHz
  28. * 7 = 1000 MHz
  29. * 9 = 1200 MHz
  30. * 12 = 1500 MHz
  31. * 13 = 1600 MHz
  32. * 14 = 1800 MHz
  33. * 15 = 2000 MHz
  34. * others reserved.
  35. *
  36. * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
  37. * 1 = (1/2) * CPU
  38. * 3 = (1/3) * CPU
  39. * 5 = (1/4) * CPU
  40. * others reserved.
  41. *
  42. * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
  43. * 2 = (1/2) * CPU
  44. * 4 = (1/3) * CPU
  45. * 6 = (1/4) * CPU
  46. * 7 = (2/9) * CPU
  47. * 8 = (1/5) * CPU
  48. * 9 = (1/6) * CPU
  49. * others reserved.
  50. *
  51. * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
  52. * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
  53. * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
  54. * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
  55. * others reserved.
  56. *
  57. * SAR0[21] : TCLK frequency
  58. * 0 = 200 MHz
  59. * 1 = 166 MHz
  60. * others reserved.
  61. */
  62. #define SAR_KIRKWOOD_CPU_FREQ(x) \
  63. (((x & (1 << 1)) >> 1) | \
  64. ((x & (1 << 22)) >> 21) | \
  65. ((x & (3 << 3)) >> 1))
  66. #define SAR_KIRKWOOD_L2_RATIO(x) \
  67. (((x & (3 << 9)) >> 9) | \
  68. (((x & (1 << 19)) >> 17)))
  69. #define SAR_KIRKWOOD_DDR_RATIO 5
  70. #define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
  71. #define SAR_MV88F6180_CLK 2
  72. #define SAR_MV88F6180_CLK_MASK 0x7
  73. #define SAR_KIRKWOOD_TCLK_FREQ 21
  74. #define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
  75. enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
  76. static const struct coreclk_ratio kirkwood_coreclk_ratios[] __initconst = {
  77. { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
  78. { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
  79. };
  80. static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
  81. {
  82. u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
  83. SAR_KIRKWOOD_TCLK_FREQ_MASK;
  84. return (opt) ? 166666667 : 200000000;
  85. }
  86. static const u32 kirkwood_cpu_freqs[] __initconst = {
  87. 0, 0, 0, 0,
  88. 600000000,
  89. 0,
  90. 800000000,
  91. 1000000000,
  92. 0,
  93. 1200000000,
  94. 0, 0,
  95. 1500000000,
  96. 1600000000,
  97. 1800000000,
  98. 2000000000
  99. };
  100. static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
  101. {
  102. u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
  103. return kirkwood_cpu_freqs[opt];
  104. }
  105. static const int kirkwood_cpu_l2_ratios[8][2] __initconst = {
  106. { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
  107. { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
  108. };
  109. static const int kirkwood_cpu_ddr_ratios[16][2] __initconst = {
  110. { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
  111. { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
  112. { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
  113. { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
  114. };
  115. static void __init kirkwood_get_clk_ratio(
  116. void __iomem *sar, int id, int *mult, int *div)
  117. {
  118. switch (id) {
  119. case KIRKWOOD_CPU_TO_L2:
  120. {
  121. u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
  122. *mult = kirkwood_cpu_l2_ratios[opt][0];
  123. *div = kirkwood_cpu_l2_ratios[opt][1];
  124. break;
  125. }
  126. case KIRKWOOD_CPU_TO_DDR:
  127. {
  128. u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
  129. SAR_KIRKWOOD_DDR_RATIO_MASK;
  130. *mult = kirkwood_cpu_ddr_ratios[opt][0];
  131. *div = kirkwood_cpu_ddr_ratios[opt][1];
  132. break;
  133. }
  134. }
  135. }
  136. static const u32 mv88f6180_cpu_freqs[] __initconst = {
  137. 0, 0, 0, 0, 0,
  138. 600000000,
  139. 800000000,
  140. 1000000000
  141. };
  142. static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
  143. {
  144. u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
  145. return mv88f6180_cpu_freqs[opt];
  146. }
  147. static const int mv88f6180_cpu_ddr_ratios[8][2] __initconst = {
  148. { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
  149. { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
  150. };
  151. static void __init mv88f6180_get_clk_ratio(
  152. void __iomem *sar, int id, int *mult, int *div)
  153. {
  154. switch (id) {
  155. case KIRKWOOD_CPU_TO_L2:
  156. {
  157. /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
  158. *mult = 1;
  159. *div = 2;
  160. break;
  161. }
  162. case KIRKWOOD_CPU_TO_DDR:
  163. {
  164. u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
  165. SAR_MV88F6180_CLK_MASK;
  166. *mult = mv88f6180_cpu_ddr_ratios[opt][0];
  167. *div = mv88f6180_cpu_ddr_ratios[opt][1];
  168. break;
  169. }
  170. }
  171. }
  172. static u32 __init mv98dx1135_get_tclk_freq(void __iomem *sar)
  173. {
  174. return 166666667;
  175. }
  176. static const struct coreclk_soc_desc kirkwood_coreclks = {
  177. .get_tclk_freq = kirkwood_get_tclk_freq,
  178. .get_cpu_freq = kirkwood_get_cpu_freq,
  179. .get_clk_ratio = kirkwood_get_clk_ratio,
  180. .ratios = kirkwood_coreclk_ratios,
  181. .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
  182. };
  183. static const struct coreclk_soc_desc mv88f6180_coreclks = {
  184. .get_tclk_freq = kirkwood_get_tclk_freq,
  185. .get_cpu_freq = mv88f6180_get_cpu_freq,
  186. .get_clk_ratio = mv88f6180_get_clk_ratio,
  187. .ratios = kirkwood_coreclk_ratios,
  188. .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
  189. };
  190. static const struct coreclk_soc_desc mv98dx1135_coreclks = {
  191. .get_tclk_freq = mv98dx1135_get_tclk_freq,
  192. .get_cpu_freq = kirkwood_get_cpu_freq,
  193. .get_clk_ratio = kirkwood_get_clk_ratio,
  194. .ratios = kirkwood_coreclk_ratios,
  195. .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
  196. };
  197. /*
  198. * Clock Gating Control
  199. */
  200. static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = {
  201. { "ge0", NULL, 0, 0 },
  202. { "pex0", NULL, 2, 0 },
  203. { "usb0", NULL, 3, 0 },
  204. { "sdio", NULL, 4, 0 },
  205. { "tsu", NULL, 5, 0 },
  206. { "runit", NULL, 7, 0 },
  207. { "xor0", NULL, 8, 0 },
  208. { "audio", NULL, 9, 0 },
  209. { "sata0", NULL, 14, 0 },
  210. { "sata1", NULL, 15, 0 },
  211. { "xor1", NULL, 16, 0 },
  212. { "crypto", NULL, 17, 0 },
  213. { "pex1", NULL, 18, 0 },
  214. { "ge1", NULL, 19, 0 },
  215. { "tdm", NULL, 20, 0 },
  216. { }
  217. };
  218. /*
  219. * Clock Muxing Control
  220. */
  221. struct clk_muxing_soc_desc {
  222. const char *name;
  223. const char **parents;
  224. int num_parents;
  225. int shift;
  226. int width;
  227. unsigned long flags;
  228. };
  229. struct clk_muxing_ctrl {
  230. spinlock_t *lock;
  231. struct clk **muxes;
  232. int num_muxes;
  233. };
  234. static const char *powersave_parents[] = {
  235. "cpuclk",
  236. "ddrclk",
  237. };
  238. static const struct clk_muxing_soc_desc kirkwood_mux_desc[] __initconst = {
  239. { "powersave", powersave_parents, ARRAY_SIZE(powersave_parents),
  240. 11, 1, 0 },
  241. { }
  242. };
  243. static struct clk *clk_muxing_get_src(
  244. struct of_phandle_args *clkspec, void *data)
  245. {
  246. struct clk_muxing_ctrl *ctrl = (struct clk_muxing_ctrl *)data;
  247. int n;
  248. if (clkspec->args_count < 1)
  249. return ERR_PTR(-EINVAL);
  250. for (n = 0; n < ctrl->num_muxes; n++) {
  251. struct clk_mux *mux =
  252. to_clk_mux(__clk_get_hw(ctrl->muxes[n]));
  253. if (clkspec->args[0] == mux->shift)
  254. return ctrl->muxes[n];
  255. }
  256. return ERR_PTR(-ENODEV);
  257. }
  258. static void __init kirkwood_clk_muxing_setup(struct device_node *np,
  259. const struct clk_muxing_soc_desc *desc)
  260. {
  261. struct clk_muxing_ctrl *ctrl;
  262. void __iomem *base;
  263. int n;
  264. base = of_iomap(np, 0);
  265. if (WARN_ON(!base))
  266. return;
  267. ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
  268. if (WARN_ON(!ctrl))
  269. goto ctrl_out;
  270. /* lock must already be initialized */
  271. ctrl->lock = &ctrl_gating_lock;
  272. /* Count, allocate, and register clock muxes */
  273. for (n = 0; desc[n].name;)
  274. n++;
  275. ctrl->num_muxes = n;
  276. ctrl->muxes = kcalloc(ctrl->num_muxes, sizeof(struct clk *),
  277. GFP_KERNEL);
  278. if (WARN_ON(!ctrl->muxes))
  279. goto muxes_out;
  280. for (n = 0; n < ctrl->num_muxes; n++) {
  281. ctrl->muxes[n] = clk_register_mux(NULL, desc[n].name,
  282. desc[n].parents, desc[n].num_parents,
  283. desc[n].flags, base, desc[n].shift,
  284. desc[n].width, desc[n].flags, ctrl->lock);
  285. WARN_ON(IS_ERR(ctrl->muxes[n]));
  286. }
  287. of_clk_add_provider(np, clk_muxing_get_src, ctrl);
  288. return;
  289. muxes_out:
  290. kfree(ctrl);
  291. ctrl_out:
  292. iounmap(base);
  293. }
  294. static void __init kirkwood_clk_init(struct device_node *np)
  295. {
  296. struct device_node *cgnp =
  297. of_find_compatible_node(NULL, NULL, "marvell,kirkwood-gating-clock");
  298. if (of_device_is_compatible(np, "marvell,mv88f6180-core-clock"))
  299. mvebu_coreclk_setup(np, &mv88f6180_coreclks);
  300. else if (of_device_is_compatible(np, "marvell,mv98dx1135-core-clock"))
  301. mvebu_coreclk_setup(np, &mv98dx1135_coreclks);
  302. else
  303. mvebu_coreclk_setup(np, &kirkwood_coreclks);
  304. if (cgnp) {
  305. mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc);
  306. kirkwood_clk_muxing_setup(cgnp, kirkwood_mux_desc);
  307. of_node_put(cgnp);
  308. }
  309. }
  310. CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock",
  311. kirkwood_clk_init);
  312. CLK_OF_DECLARE(mv88f6180_clk, "marvell,mv88f6180-core-clock",
  313. kirkwood_clk_init);
  314. CLK_OF_DECLARE(98dx1135_clk, "marvell,mv98dx1135-core-clock",
  315. kirkwood_clk_init);