dove.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Dove SoC clocks
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  9. * Andrew Lunn <andrew@lunn.ch>
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/io.h>
  15. #include <linux/of.h>
  16. #include "common.h"
  17. #include "dove-divider.h"
  18. /*
  19. * Core Clocks
  20. *
  21. * Dove PLL sample-at-reset configuration
  22. *
  23. * SAR0[8:5] : CPU frequency
  24. * 5 = 1000 MHz
  25. * 6 = 933 MHz
  26. * 7 = 933 MHz
  27. * 8 = 800 MHz
  28. * 9 = 800 MHz
  29. * 10 = 800 MHz
  30. * 11 = 1067 MHz
  31. * 12 = 667 MHz
  32. * 13 = 533 MHz
  33. * 14 = 400 MHz
  34. * 15 = 333 MHz
  35. * others reserved.
  36. *
  37. * SAR0[11:9] : CPU to L2 Clock divider ratio
  38. * 0 = (1/1) * CPU
  39. * 2 = (1/2) * CPU
  40. * 4 = (1/3) * CPU
  41. * 6 = (1/4) * CPU
  42. * others reserved.
  43. *
  44. * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
  45. * 0 = (1/1) * CPU
  46. * 2 = (1/2) * CPU
  47. * 3 = (2/5) * CPU
  48. * 4 = (1/3) * CPU
  49. * 6 = (1/4) * CPU
  50. * 8 = (1/5) * CPU
  51. * 10 = (1/6) * CPU
  52. * 12 = (1/7) * CPU
  53. * 14 = (1/8) * CPU
  54. * 15 = (1/10) * CPU
  55. * others reserved.
  56. *
  57. * SAR0[24:23] : TCLK frequency
  58. * 0 = 166 MHz
  59. * 1 = 125 MHz
  60. * others reserved.
  61. */
  62. #define SAR_DOVE_CPU_FREQ 5
  63. #define SAR_DOVE_CPU_FREQ_MASK 0xf
  64. #define SAR_DOVE_L2_RATIO 9
  65. #define SAR_DOVE_L2_RATIO_MASK 0x7
  66. #define SAR_DOVE_DDR_RATIO 12
  67. #define SAR_DOVE_DDR_RATIO_MASK 0xf
  68. #define SAR_DOVE_TCLK_FREQ 23
  69. #define SAR_DOVE_TCLK_FREQ_MASK 0x3
  70. enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
  71. static const struct coreclk_ratio dove_coreclk_ratios[] __initconst = {
  72. { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
  73. { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
  74. };
  75. static const u32 dove_tclk_freqs[] __initconst = {
  76. 166666667,
  77. 125000000,
  78. 0, 0
  79. };
  80. static u32 __init dove_get_tclk_freq(void __iomem *sar)
  81. {
  82. u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
  83. SAR_DOVE_TCLK_FREQ_MASK;
  84. return dove_tclk_freqs[opt];
  85. }
  86. static const u32 dove_cpu_freqs[] __initconst = {
  87. 0, 0, 0, 0, 0,
  88. 1000000000,
  89. 933333333, 933333333,
  90. 800000000, 800000000, 800000000,
  91. 1066666667,
  92. 666666667,
  93. 533333333,
  94. 400000000,
  95. 333333333
  96. };
  97. static u32 __init dove_get_cpu_freq(void __iomem *sar)
  98. {
  99. u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
  100. SAR_DOVE_CPU_FREQ_MASK;
  101. return dove_cpu_freqs[opt];
  102. }
  103. static const int dove_cpu_l2_ratios[8][2] __initconst = {
  104. { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
  105. { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
  106. };
  107. static const int dove_cpu_ddr_ratios[16][2] __initconst = {
  108. { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
  109. { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
  110. { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
  111. { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
  112. };
  113. static void __init dove_get_clk_ratio(
  114. void __iomem *sar, int id, int *mult, int *div)
  115. {
  116. switch (id) {
  117. case DOVE_CPU_TO_L2:
  118. {
  119. u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
  120. SAR_DOVE_L2_RATIO_MASK;
  121. *mult = dove_cpu_l2_ratios[opt][0];
  122. *div = dove_cpu_l2_ratios[opt][1];
  123. break;
  124. }
  125. case DOVE_CPU_TO_DDR:
  126. {
  127. u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
  128. SAR_DOVE_DDR_RATIO_MASK;
  129. *mult = dove_cpu_ddr_ratios[opt][0];
  130. *div = dove_cpu_ddr_ratios[opt][1];
  131. break;
  132. }
  133. }
  134. }
  135. static const struct coreclk_soc_desc dove_coreclks = {
  136. .get_tclk_freq = dove_get_tclk_freq,
  137. .get_cpu_freq = dove_get_cpu_freq,
  138. .get_clk_ratio = dove_get_clk_ratio,
  139. .ratios = dove_coreclk_ratios,
  140. .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
  141. };
  142. /*
  143. * Clock Gating Control
  144. */
  145. static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = {
  146. { "usb0", NULL, 0, 0 },
  147. { "usb1", NULL, 1, 0 },
  148. { "ge", "gephy", 2, 0 },
  149. { "sata", NULL, 3, 0 },
  150. { "pex0", NULL, 4, 0 },
  151. { "pex1", NULL, 5, 0 },
  152. { "sdio0", NULL, 8, 0 },
  153. { "sdio1", NULL, 9, 0 },
  154. { "nand", NULL, 10, 0 },
  155. { "camera", NULL, 11, 0 },
  156. { "i2s0", NULL, 12, 0 },
  157. { "i2s1", NULL, 13, 0 },
  158. { "crypto", NULL, 15, 0 },
  159. { "ac97", NULL, 21, 0 },
  160. { "pdma", NULL, 22, 0 },
  161. { "xor0", NULL, 23, 0 },
  162. { "xor1", NULL, 24, 0 },
  163. { "gephy", NULL, 30, 0 },
  164. { }
  165. };
  166. static void __init dove_clk_init(struct device_node *np)
  167. {
  168. struct device_node *cgnp =
  169. of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock");
  170. struct device_node *ddnp =
  171. of_find_compatible_node(NULL, NULL, "marvell,dove-divider-clock");
  172. mvebu_coreclk_setup(np, &dove_coreclks);
  173. if (ddnp) {
  174. dove_divider_clk_init(ddnp);
  175. of_node_put(ddnp);
  176. }
  177. if (cgnp) {
  178. mvebu_clk_gating_setup(cgnp, dove_gating_desc);
  179. of_node_put(cgnp);
  180. }
  181. }
  182. CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);