dove-divider.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Dove PMU Core PLL divider driver
  4. *
  5. * Cleaned up by substantially rewriting, and converted to DT by
  6. * Russell King. Origin is not known.
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/delay.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include "dove-divider.h"
  15. struct dove_clk {
  16. const char *name;
  17. struct clk_hw hw;
  18. void __iomem *base;
  19. spinlock_t *lock;
  20. u8 div_bit_start;
  21. u8 div_bit_end;
  22. u8 div_bit_load;
  23. u8 div_bit_size;
  24. u32 *divider_table;
  25. };
  26. enum {
  27. DIV_CTRL0 = 0,
  28. DIV_CTRL1 = 4,
  29. DIV_CTRL1_N_RESET_MASK = BIT(10),
  30. };
  31. #define to_dove_clk(hw) container_of(hw, struct dove_clk, hw)
  32. static void dove_load_divider(void __iomem *base, u32 val, u32 mask, u32 load)
  33. {
  34. u32 v;
  35. v = readl_relaxed(base + DIV_CTRL1) | DIV_CTRL1_N_RESET_MASK;
  36. writel_relaxed(v, base + DIV_CTRL1);
  37. v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val;
  38. writel_relaxed(v, base + DIV_CTRL0);
  39. writel_relaxed(v | load, base + DIV_CTRL0);
  40. ndelay(250);
  41. writel_relaxed(v, base + DIV_CTRL0);
  42. }
  43. static unsigned int dove_get_divider(struct dove_clk *dc)
  44. {
  45. unsigned int divider;
  46. u32 val;
  47. val = readl_relaxed(dc->base + DIV_CTRL0);
  48. val >>= dc->div_bit_start;
  49. divider = val & ~(~0 << dc->div_bit_size);
  50. if (dc->divider_table)
  51. divider = dc->divider_table[divider];
  52. return divider;
  53. }
  54. static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,
  55. unsigned long parent_rate, bool set)
  56. {
  57. unsigned int divider, max;
  58. divider = DIV_ROUND_CLOSEST(parent_rate, rate);
  59. if (dc->divider_table) {
  60. unsigned int i;
  61. for (i = 0; dc->divider_table[i]; i++)
  62. if (divider == dc->divider_table[i]) {
  63. divider = i;
  64. break;
  65. }
  66. if (!dc->divider_table[i])
  67. return -EINVAL;
  68. } else {
  69. max = 1 << dc->div_bit_size;
  70. if (set && (divider == 0 || divider >= max))
  71. return -EINVAL;
  72. if (divider >= max)
  73. divider = max - 1;
  74. else if (divider == 0)
  75. divider = 1;
  76. }
  77. return divider;
  78. }
  79. static unsigned long dove_recalc_rate(struct clk_hw *hw, unsigned long parent)
  80. {
  81. struct dove_clk *dc = to_dove_clk(hw);
  82. unsigned int divider = dove_get_divider(dc);
  83. unsigned long rate = DIV_ROUND_CLOSEST(parent, divider);
  84. pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
  85. __func__, dc->name, divider, parent, rate);
  86. return rate;
  87. }
  88. static long dove_round_rate(struct clk_hw *hw, unsigned long rate,
  89. unsigned long *parent)
  90. {
  91. struct dove_clk *dc = to_dove_clk(hw);
  92. unsigned long parent_rate = *parent;
  93. int divider;
  94. divider = dove_calc_divider(dc, rate, parent_rate, false);
  95. if (divider < 0)
  96. return divider;
  97. rate = DIV_ROUND_CLOSEST(parent_rate, divider);
  98. pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
  99. __func__, dc->name, divider, parent_rate, rate);
  100. return rate;
  101. }
  102. static int dove_set_clock(struct clk_hw *hw, unsigned long rate,
  103. unsigned long parent_rate)
  104. {
  105. struct dove_clk *dc = to_dove_clk(hw);
  106. u32 mask, load, div;
  107. int divider;
  108. divider = dove_calc_divider(dc, rate, parent_rate, true);
  109. if (divider < 0)
  110. return divider;
  111. pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",
  112. __func__, dc->name, divider, parent_rate, rate);
  113. div = (u32)divider << dc->div_bit_start;
  114. mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start;
  115. load = BIT(dc->div_bit_load);
  116. spin_lock(dc->lock);
  117. dove_load_divider(dc->base, div, mask, load);
  118. spin_unlock(dc->lock);
  119. return 0;
  120. }
  121. static const struct clk_ops dove_divider_ops = {
  122. .set_rate = dove_set_clock,
  123. .round_rate = dove_round_rate,
  124. .recalc_rate = dove_recalc_rate,
  125. };
  126. static struct clk *clk_register_dove_divider(struct device *dev,
  127. struct dove_clk *dc, const char **parent_names, size_t num_parents,
  128. void __iomem *base)
  129. {
  130. char name[32];
  131. struct clk_init_data init = {
  132. .name = name,
  133. .ops = &dove_divider_ops,
  134. .parent_names = parent_names,
  135. .num_parents = num_parents,
  136. };
  137. strlcpy(name, dc->name, sizeof(name));
  138. dc->hw.init = &init;
  139. dc->base = base;
  140. dc->div_bit_size = dc->div_bit_end - dc->div_bit_start + 1;
  141. return clk_register(dev, &dc->hw);
  142. }
  143. static DEFINE_SPINLOCK(dove_divider_lock);
  144. static u32 axi_divider[] = {-1, 2, 1, 3, 4, 6, 5, 7, 8, 10, 9, 0};
  145. static struct dove_clk dove_hw_clocks[4] = {
  146. {
  147. .name = "axi",
  148. .lock = &dove_divider_lock,
  149. .div_bit_start = 1,
  150. .div_bit_end = 6,
  151. .div_bit_load = 7,
  152. .divider_table = axi_divider,
  153. }, {
  154. .name = "gpu",
  155. .lock = &dove_divider_lock,
  156. .div_bit_start = 8,
  157. .div_bit_end = 13,
  158. .div_bit_load = 14,
  159. }, {
  160. .name = "vmeta",
  161. .lock = &dove_divider_lock,
  162. .div_bit_start = 15,
  163. .div_bit_end = 20,
  164. .div_bit_load = 21,
  165. }, {
  166. .name = "lcd",
  167. .lock = &dove_divider_lock,
  168. .div_bit_start = 22,
  169. .div_bit_end = 27,
  170. .div_bit_load = 28,
  171. },
  172. };
  173. static const char *core_pll[] = {
  174. "core-pll",
  175. };
  176. static int dove_divider_init(struct device *dev, void __iomem *base,
  177. struct clk **clks)
  178. {
  179. struct clk *clk;
  180. int i;
  181. /*
  182. * Create the core PLL clock. We treat this as a fixed rate
  183. * clock as we don't know any better, and documentation is sparse.
  184. */
  185. clk = clk_register_fixed_rate(dev, core_pll[0], NULL, 0, 2000000000UL);
  186. if (IS_ERR(clk))
  187. return PTR_ERR(clk);
  188. for (i = 0; i < ARRAY_SIZE(dove_hw_clocks); i++)
  189. clks[i] = clk_register_dove_divider(dev, &dove_hw_clocks[i],
  190. core_pll,
  191. ARRAY_SIZE(core_pll), base);
  192. return 0;
  193. }
  194. static struct clk *dove_divider_clocks[4];
  195. static struct clk_onecell_data dove_divider_data = {
  196. .clks = dove_divider_clocks,
  197. .clk_num = ARRAY_SIZE(dove_divider_clocks),
  198. };
  199. void __init dove_divider_clk_init(struct device_node *np)
  200. {
  201. void __iomem *base;
  202. base = of_iomap(np, 0);
  203. if (WARN_ON(!base))
  204. return;
  205. if (WARN_ON(dove_divider_init(NULL, base, dove_divider_clocks))) {
  206. iounmap(base);
  207. return;
  208. }
  209. of_clk_add_provider(np, of_clk_src_onecell_get, &dove_divider_data);
  210. }