common.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Marvell EBU SoC common clock handling
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  9. * Andrew Lunn <andrew@lunn.ch>
  10. *
  11. */
  12. #ifndef __CLK_MVEBU_COMMON_H_
  13. #define __CLK_MVEBU_COMMON_H_
  14. #include <linux/kernel.h>
  15. extern spinlock_t ctrl_gating_lock;
  16. struct device_node;
  17. struct coreclk_ratio {
  18. int id;
  19. const char *name;
  20. };
  21. struct coreclk_soc_desc {
  22. u32 (*get_tclk_freq)(void __iomem *sar);
  23. u32 (*get_cpu_freq)(void __iomem *sar);
  24. void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
  25. u32 (*get_refclk_freq)(void __iomem *sar);
  26. bool (*is_sscg_enabled)(void __iomem *sar);
  27. u32 (*fix_sscg_deviation)(u32 system_clk);
  28. const struct coreclk_ratio *ratios;
  29. int num_ratios;
  30. };
  31. struct clk_gating_soc_desc {
  32. const char *name;
  33. const char *parent;
  34. int bit_idx;
  35. unsigned long flags;
  36. };
  37. void __init mvebu_coreclk_setup(struct device_node *np,
  38. const struct coreclk_soc_desc *desc);
  39. void __init mvebu_clk_gating_setup(struct device_node *np,
  40. const struct clk_gating_soc_desc *desc);
  41. /*
  42. * This function is shared among the Kirkwood, Armada 370, Armada XP
  43. * and Armada 375 SoC
  44. */
  45. u32 kirkwood_fix_sscg_deviation(u32 system_clk);
  46. #endif