clk-cpu.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell MVEBU CPU clock handling.
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. *
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/slab.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/of_address.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/delay.h>
  18. #include <linux/mvebu-pmsu.h>
  19. #include <asm/smp_plat.h>
  20. #define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
  21. #define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL 0xff
  22. #define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT 8
  23. #define SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET 0x8
  24. #define SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT 16
  25. #define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
  26. #define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
  27. #define PMU_DFS_RATIO_SHIFT 16
  28. #define PMU_DFS_RATIO_MASK 0x3F
  29. #define MAX_CPU 4
  30. struct cpu_clk {
  31. struct clk_hw hw;
  32. int cpu;
  33. const char *clk_name;
  34. const char *parent_name;
  35. void __iomem *reg_base;
  36. void __iomem *pmu_dfs;
  37. };
  38. static struct clk **clks;
  39. static struct clk_onecell_data clk_data;
  40. #define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
  41. static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
  42. unsigned long parent_rate)
  43. {
  44. struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
  45. u32 reg, div;
  46. reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
  47. div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
  48. return parent_rate / div;
  49. }
  50. static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
  51. unsigned long *parent_rate)
  52. {
  53. /* Valid ratio are 1:1, 1:2 and 1:3 */
  54. u32 div;
  55. div = *parent_rate / rate;
  56. if (div == 0)
  57. div = 1;
  58. else if (div > 3)
  59. div = 3;
  60. return *parent_rate / div;
  61. }
  62. static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate,
  63. unsigned long parent_rate)
  64. {
  65. struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
  66. u32 reg, div;
  67. u32 reload_mask;
  68. div = parent_rate / rate;
  69. reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
  70. & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
  71. | (div << (cpuclk->cpu * 8));
  72. writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
  73. /* Set clock divider reload smooth bit mask */
  74. reload_mask = 1 << (20 + cpuclk->cpu);
  75. reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
  76. | reload_mask;
  77. writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
  78. /* Now trigger the clock update */
  79. reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
  80. | 1 << 24;
  81. writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
  82. /* Wait for clocks to settle down then clear reload request */
  83. udelay(1000);
  84. reg &= ~(reload_mask | 1 << 24);
  85. writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
  86. udelay(1000);
  87. return 0;
  88. }
  89. static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate,
  90. unsigned long parent_rate)
  91. {
  92. u32 reg;
  93. unsigned long fabric_div, target_div, cur_rate;
  94. struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
  95. /*
  96. * PMU DFS registers are not mapped, Device Tree does not
  97. * describes them. We cannot change the frequency dynamically.
  98. */
  99. if (!cpuclk->pmu_dfs)
  100. return -ENODEV;
  101. cur_rate = clk_hw_get_rate(hwclk);
  102. reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET);
  103. fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &
  104. SYS_CTRL_CLK_DIVIDER_MASK;
  105. /* Frequency is going up */
  106. if (rate == 2 * cur_rate)
  107. target_div = fabric_div / 2;
  108. /* Frequency is going down */
  109. else
  110. target_div = fabric_div;
  111. if (target_div == 0)
  112. target_div = 1;
  113. reg = readl(cpuclk->pmu_dfs);
  114. reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT);
  115. reg |= (target_div << PMU_DFS_RATIO_SHIFT);
  116. writel(reg, cpuclk->pmu_dfs);
  117. reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
  118. reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL <<
  119. SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT);
  120. writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
  121. return mvebu_pmsu_dfs_request(cpuclk->cpu);
  122. }
  123. static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
  124. unsigned long parent_rate)
  125. {
  126. if (__clk_is_enabled(hwclk->clk))
  127. return clk_cpu_on_set_rate(hwclk, rate, parent_rate);
  128. else
  129. return clk_cpu_off_set_rate(hwclk, rate, parent_rate);
  130. }
  131. static const struct clk_ops cpu_ops = {
  132. .recalc_rate = clk_cpu_recalc_rate,
  133. .round_rate = clk_cpu_round_rate,
  134. .set_rate = clk_cpu_set_rate,
  135. };
  136. static void __init of_cpu_clk_setup(struct device_node *node)
  137. {
  138. struct cpu_clk *cpuclk;
  139. void __iomem *clock_complex_base = of_iomap(node, 0);
  140. void __iomem *pmu_dfs_base = of_iomap(node, 1);
  141. int ncpus = 0;
  142. struct device_node *dn;
  143. if (clock_complex_base == NULL) {
  144. pr_err("%s: clock-complex base register not set\n",
  145. __func__);
  146. return;
  147. }
  148. if (pmu_dfs_base == NULL)
  149. pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n",
  150. __func__);
  151. for_each_of_cpu_node(dn)
  152. ncpus++;
  153. cpuclk = kcalloc(ncpus, sizeof(*cpuclk), GFP_KERNEL);
  154. if (WARN_ON(!cpuclk))
  155. goto cpuclk_out;
  156. clks = kcalloc(ncpus, sizeof(*clks), GFP_KERNEL);
  157. if (WARN_ON(!clks))
  158. goto clks_out;
  159. for_each_of_cpu_node(dn) {
  160. struct clk_init_data init;
  161. struct clk *clk;
  162. char *clk_name = kzalloc(5, GFP_KERNEL);
  163. int cpu, err;
  164. if (WARN_ON(!clk_name))
  165. goto bail_out;
  166. err = of_property_read_u32(dn, "reg", &cpu);
  167. if (WARN_ON(err))
  168. goto bail_out;
  169. sprintf(clk_name, "cpu%d", cpu);
  170. cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0);
  171. cpuclk[cpu].clk_name = clk_name;
  172. cpuclk[cpu].cpu = cpu;
  173. cpuclk[cpu].reg_base = clock_complex_base;
  174. if (pmu_dfs_base)
  175. cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu;
  176. cpuclk[cpu].hw.init = &init;
  177. init.name = cpuclk[cpu].clk_name;
  178. init.ops = &cpu_ops;
  179. init.flags = 0;
  180. init.parent_names = &cpuclk[cpu].parent_name;
  181. init.num_parents = 1;
  182. clk = clk_register(NULL, &cpuclk[cpu].hw);
  183. if (WARN_ON(IS_ERR(clk)))
  184. goto bail_out;
  185. clks[cpu] = clk;
  186. }
  187. clk_data.clk_num = MAX_CPU;
  188. clk_data.clks = clks;
  189. of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
  190. return;
  191. bail_out:
  192. kfree(clks);
  193. while(ncpus--)
  194. kfree(cpuclk[ncpus].clk_name);
  195. clks_out:
  196. kfree(cpuclk);
  197. cpuclk_out:
  198. iounmap(clock_complex_base);
  199. }
  200. CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
  201. of_cpu_clk_setup);
  202. static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
  203. {
  204. of_clk_add_provider(node, of_clk_src_simple_get, NULL);
  205. }
  206. CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
  207. of_mv98dx3236_cpu_clk_setup);