armada-xp.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Armada XP SoC clocks
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  9. * Andrew Lunn <andrew@lunn.ch>
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/io.h>
  15. #include <linux/of.h>
  16. #include "common.h"
  17. /*
  18. * Core Clocks
  19. *
  20. * Armada XP Sample At Reset is a 64 bit bitfiled split in two
  21. * register of 32 bits
  22. */
  23. #define SARL 0 /* Low part [0:31] */
  24. #define SARL_AXP_PCLK_FREQ_OPT 21
  25. #define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
  26. #define SARL_AXP_FAB_FREQ_OPT 24
  27. #define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
  28. #define SARH 4 /* High part [32:63] */
  29. #define SARH_AXP_PCLK_FREQ_OPT (52-32)
  30. #define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
  31. #define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
  32. #define SARH_AXP_FAB_FREQ_OPT (51-32)
  33. #define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
  34. #define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
  35. enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
  36. static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {
  37. { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
  38. { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
  39. { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
  40. };
  41. /* Armada XP TCLK frequency is fixed to 250MHz */
  42. static u32 __init axp_get_tclk_freq(void __iomem *sar)
  43. {
  44. return 250000000;
  45. }
  46. static const u32 axp_cpu_freqs[] __initconst = {
  47. 1000000000,
  48. 1066000000,
  49. 1200000000,
  50. 1333000000,
  51. 1500000000,
  52. 1666000000,
  53. 1800000000,
  54. 2000000000,
  55. 667000000,
  56. 0,
  57. 800000000,
  58. 1600000000,
  59. };
  60. static u32 __init axp_get_cpu_freq(void __iomem *sar)
  61. {
  62. u32 cpu_freq;
  63. u8 cpu_freq_select = 0;
  64. cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
  65. SARL_AXP_PCLK_FREQ_OPT_MASK);
  66. /*
  67. * The upper bit is not contiguous to the other ones and
  68. * located in the high part of the SAR registers
  69. */
  70. cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
  71. SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
  72. if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
  73. pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
  74. cpu_freq = 0;
  75. } else
  76. cpu_freq = axp_cpu_freqs[cpu_freq_select];
  77. return cpu_freq;
  78. }
  79. static const int axp_nbclk_ratios[32][2] __initconst = {
  80. {0, 1}, {1, 2}, {2, 2}, {2, 2},
  81. {1, 2}, {1, 2}, {1, 1}, {2, 3},
  82. {0, 1}, {1, 2}, {2, 4}, {0, 1},
  83. {1, 2}, {0, 1}, {0, 1}, {2, 2},
  84. {0, 1}, {0, 1}, {0, 1}, {1, 1},
  85. {2, 3}, {0, 1}, {0, 1}, {0, 1},
  86. {0, 1}, {0, 1}, {0, 1}, {1, 1},
  87. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  88. };
  89. static const int axp_hclk_ratios[32][2] __initconst = {
  90. {0, 1}, {1, 2}, {2, 6}, {2, 3},
  91. {1, 3}, {1, 4}, {1, 2}, {2, 6},
  92. {0, 1}, {1, 6}, {2, 10}, {0, 1},
  93. {1, 4}, {0, 1}, {0, 1}, {2, 5},
  94. {0, 1}, {0, 1}, {0, 1}, {1, 2},
  95. {2, 6}, {0, 1}, {0, 1}, {0, 1},
  96. {0, 1}, {0, 1}, {0, 1}, {1, 1},
  97. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  98. };
  99. static const int axp_dramclk_ratios[32][2] __initconst = {
  100. {0, 1}, {1, 2}, {2, 3}, {2, 3},
  101. {1, 3}, {1, 2}, {1, 2}, {2, 6},
  102. {0, 1}, {1, 3}, {2, 5}, {0, 1},
  103. {1, 4}, {0, 1}, {0, 1}, {2, 5},
  104. {0, 1}, {0, 1}, {0, 1}, {1, 1},
  105. {2, 3}, {0, 1}, {0, 1}, {0, 1},
  106. {0, 1}, {0, 1}, {0, 1}, {1, 1},
  107. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  108. };
  109. static void __init axp_get_clk_ratio(
  110. void __iomem *sar, int id, int *mult, int *div)
  111. {
  112. u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
  113. SARL_AXP_FAB_FREQ_OPT_MASK);
  114. /*
  115. * The upper bit is not contiguous to the other ones and
  116. * located in the high part of the SAR registers
  117. */
  118. opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
  119. SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
  120. switch (id) {
  121. case AXP_CPU_TO_NBCLK:
  122. *mult = axp_nbclk_ratios[opt][0];
  123. *div = axp_nbclk_ratios[opt][1];
  124. break;
  125. case AXP_CPU_TO_HCLK:
  126. *mult = axp_hclk_ratios[opt][0];
  127. *div = axp_hclk_ratios[opt][1];
  128. break;
  129. case AXP_CPU_TO_DRAMCLK:
  130. *mult = axp_dramclk_ratios[opt][0];
  131. *div = axp_dramclk_ratios[opt][1];
  132. break;
  133. }
  134. }
  135. static const struct coreclk_soc_desc axp_coreclks = {
  136. .get_tclk_freq = axp_get_tclk_freq,
  137. .get_cpu_freq = axp_get_cpu_freq,
  138. .get_clk_ratio = axp_get_clk_ratio,
  139. .ratios = axp_coreclk_ratios,
  140. .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
  141. };
  142. /*
  143. * Clock Gating Control
  144. */
  145. static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
  146. { "audio", NULL, 0, 0 },
  147. { "ge3", NULL, 1, 0 },
  148. { "ge2", NULL, 2, 0 },
  149. { "ge1", NULL, 3, 0 },
  150. { "ge0", NULL, 4, 0 },
  151. { "pex00", NULL, 5, 0 },
  152. { "pex01", NULL, 6, 0 },
  153. { "pex02", NULL, 7, 0 },
  154. { "pex03", NULL, 8, 0 },
  155. { "pex10", NULL, 9, 0 },
  156. { "pex11", NULL, 10, 0 },
  157. { "pex12", NULL, 11, 0 },
  158. { "pex13", NULL, 12, 0 },
  159. { "bp", NULL, 13, 0 },
  160. { "sata0lnk", NULL, 14, 0 },
  161. { "sata0", "sata0lnk", 15, 0 },
  162. { "lcd", NULL, 16, 0 },
  163. { "sdio", NULL, 17, 0 },
  164. { "usb0", NULL, 18, 0 },
  165. { "usb1", NULL, 19, 0 },
  166. { "usb2", NULL, 20, 0 },
  167. { "xor0", NULL, 22, 0 },
  168. { "crypto", NULL, 23, 0 },
  169. { "tdm", NULL, 25, 0 },
  170. { "pex20", NULL, 26, 0 },
  171. { "pex30", NULL, 27, 0 },
  172. { "xor1", NULL, 28, 0 },
  173. { "sata1lnk", NULL, 29, 0 },
  174. { "sata1", "sata1lnk", 30, 0 },
  175. { }
  176. };
  177. static void __init axp_clk_init(struct device_node *np)
  178. {
  179. struct device_node *cgnp =
  180. of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
  181. mvebu_coreclk_setup(np, &axp_coreclks);
  182. if (cgnp) {
  183. mvebu_clk_gating_setup(cgnp, axp_gating_desc);
  184. of_node_put(cgnp);
  185. }
  186. }
  187. CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);