armada-38x.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Armada 380/385 SoC clocks
  4. *
  5. * Copyright (C) 2014 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  9. * Andrew Lunn <andrew@lunn.ch>
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/io.h>
  15. #include <linux/of.h>
  16. #include "common.h"
  17. /*
  18. * SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
  19. *
  20. * SAR[15] : TCLK frequency
  21. * 0 = 250 MHz
  22. * 1 = 200 MHz
  23. */
  24. #define SAR_A380_TCLK_FREQ_OPT 15
  25. #define SAR_A380_TCLK_FREQ_OPT_MASK 0x1
  26. #define SAR_A380_CPU_DDR_L2_FREQ_OPT 10
  27. #define SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
  28. static const u32 armada_38x_tclk_frequencies[] __initconst = {
  29. 250000000,
  30. 200000000,
  31. };
  32. static u32 __init armada_38x_get_tclk_freq(void __iomem *sar)
  33. {
  34. u8 tclk_freq_select;
  35. tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) &
  36. SAR_A380_TCLK_FREQ_OPT_MASK);
  37. return armada_38x_tclk_frequencies[tclk_freq_select];
  38. }
  39. static const u32 armada_38x_cpu_frequencies[] __initconst = {
  40. 666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
  41. 1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
  42. 1332 * 1000 * 1000, 0, 0, 0,
  43. 1600 * 1000 * 1000, 0, 0, 0,
  44. 1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
  45. };
  46. static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
  47. {
  48. u8 cpu_freq_select;
  49. cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
  50. SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
  51. if (cpu_freq_select >= ARRAY_SIZE(armada_38x_cpu_frequencies)) {
  52. pr_err("Selected CPU frequency (%d) unsupported\n",
  53. cpu_freq_select);
  54. return 0;
  55. }
  56. return armada_38x_cpu_frequencies[cpu_freq_select];
  57. }
  58. enum { A380_CPU_TO_DDR, A380_CPU_TO_L2 };
  59. static const struct coreclk_ratio armada_38x_coreclk_ratios[] __initconst = {
  60. { .id = A380_CPU_TO_L2, .name = "l2clk" },
  61. { .id = A380_CPU_TO_DDR, .name = "ddrclk" },
  62. };
  63. static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
  64. {1, 2}, {0, 1}, {1, 2}, {0, 1},
  65. {1, 2}, {0, 1}, {1, 2}, {0, 1},
  66. {1, 2}, {0, 1}, {0, 1}, {0, 1},
  67. {1, 2}, {0, 1}, {0, 1}, {0, 1},
  68. {1, 2}, {0, 1}, {0, 1}, {1, 2},
  69. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  70. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  71. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  72. };
  73. static const int armada_38x_cpu_ddr_ratios[32][2] __initconst = {
  74. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  75. {1, 2}, {0, 1}, {0, 1}, {0, 1},
  76. {1, 2}, {0, 1}, {0, 1}, {0, 1},
  77. {1, 2}, {0, 1}, {0, 1}, {0, 1},
  78. {1, 2}, {0, 1}, {0, 1}, {7, 15},
  79. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  80. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  81. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  82. };
  83. static void __init armada_38x_get_clk_ratio(
  84. void __iomem *sar, int id, int *mult, int *div)
  85. {
  86. u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
  87. SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
  88. switch (id) {
  89. case A380_CPU_TO_L2:
  90. *mult = armada_38x_cpu_l2_ratios[opt][0];
  91. *div = armada_38x_cpu_l2_ratios[opt][1];
  92. break;
  93. case A380_CPU_TO_DDR:
  94. *mult = armada_38x_cpu_ddr_ratios[opt][0];
  95. *div = armada_38x_cpu_ddr_ratios[opt][1];
  96. break;
  97. }
  98. }
  99. static const struct coreclk_soc_desc armada_38x_coreclks = {
  100. .get_tclk_freq = armada_38x_get_tclk_freq,
  101. .get_cpu_freq = armada_38x_get_cpu_freq,
  102. .get_clk_ratio = armada_38x_get_clk_ratio,
  103. .ratios = armada_38x_coreclk_ratios,
  104. .num_ratios = ARRAY_SIZE(armada_38x_coreclk_ratios),
  105. };
  106. static void __init armada_38x_coreclk_init(struct device_node *np)
  107. {
  108. mvebu_coreclk_setup(np, &armada_38x_coreclks);
  109. }
  110. CLK_OF_DECLARE(armada_38x_core_clk, "marvell,armada-380-core-clock",
  111. armada_38x_coreclk_init);
  112. /*
  113. * Clock Gating Control
  114. */
  115. static const struct clk_gating_soc_desc armada_38x_gating_desc[] __initconst = {
  116. { "audio", NULL, 0 },
  117. { "ge2", NULL, 2 },
  118. { "ge1", NULL, 3 },
  119. { "ge0", NULL, 4 },
  120. { "pex1", NULL, 5 },
  121. { "pex2", NULL, 6 },
  122. { "pex3", NULL, 7 },
  123. { "pex0", NULL, 8 },
  124. { "usb3h0", NULL, 9 },
  125. { "usb3h1", NULL, 10 },
  126. { "usb3d", NULL, 11 },
  127. { "bm", NULL, 13 },
  128. { "crypto0z", NULL, 14 },
  129. { "sata0", NULL, 15 },
  130. { "crypto1z", NULL, 16 },
  131. { "sdio", NULL, 17 },
  132. { "usb2", NULL, 18 },
  133. { "crypto1", NULL, 21 },
  134. { "xor0", NULL, 22 },
  135. { "crypto0", NULL, 23 },
  136. { "tdm", NULL, 25 },
  137. { "xor1", NULL, 28 },
  138. { "sata1", NULL, 30 },
  139. { }
  140. };
  141. static void __init armada_38x_clk_gating_init(struct device_node *np)
  142. {
  143. mvebu_clk_gating_setup(np, armada_38x_gating_desc);
  144. }
  145. CLK_OF_DECLARE(armada_38x_clk_gating, "marvell,armada-380-gating-clock",
  146. armada_38x_clk_gating_init);