armada-375.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Armada 375 SoC clocks
  4. *
  5. * Copyright (C) 2014 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  9. * Andrew Lunn <andrew@lunn.ch>
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/io.h>
  15. #include <linux/of.h>
  16. #include "common.h"
  17. /*
  18. * Core Clocks
  19. */
  20. /*
  21. * For the Armada 375 SoCs, the CPU, DDR and L2 clocks frequencies are
  22. * all modified at the same time, and not separately as for the Armada
  23. * 370 or the Armada XP SoCs.
  24. *
  25. * SAR1[21:17] : CPU frequency DDR frequency L2 frequency
  26. * 6 = 400 MHz 400 MHz 200 MHz
  27. * 15 = 600 MHz 600 MHz 300 MHz
  28. * 21 = 800 MHz 534 MHz 400 MHz
  29. * 25 = 1000 MHz 500 MHz 500 MHz
  30. * others reserved.
  31. *
  32. * SAR1[22] : TCLK frequency
  33. * 0 = 166 MHz
  34. * 1 = 200 MHz
  35. */
  36. #define SAR1_A375_TCLK_FREQ_OPT 22
  37. #define SAR1_A375_TCLK_FREQ_OPT_MASK 0x1
  38. #define SAR1_A375_CPU_DDR_L2_FREQ_OPT 17
  39. #define SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
  40. static const u32 armada_375_tclk_frequencies[] __initconst = {
  41. 166000000,
  42. 200000000,
  43. };
  44. static u32 __init armada_375_get_tclk_freq(void __iomem *sar)
  45. {
  46. u8 tclk_freq_select;
  47. tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) &
  48. SAR1_A375_TCLK_FREQ_OPT_MASK);
  49. return armada_375_tclk_frequencies[tclk_freq_select];
  50. }
  51. static const u32 armada_375_cpu_frequencies[] __initconst = {
  52. 0, 0, 0, 0, 0, 0,
  53. 400000000,
  54. 0, 0, 0, 0, 0, 0, 0, 0,
  55. 600000000,
  56. 0, 0, 0, 0, 0,
  57. 800000000,
  58. 0, 0, 0,
  59. 1000000000,
  60. };
  61. static u32 __init armada_375_get_cpu_freq(void __iomem *sar)
  62. {
  63. u8 cpu_freq_select;
  64. cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
  65. SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);
  66. if (cpu_freq_select >= ARRAY_SIZE(armada_375_cpu_frequencies)) {
  67. pr_err("Selected CPU frequency (%d) unsupported\n",
  68. cpu_freq_select);
  69. return 0;
  70. } else
  71. return armada_375_cpu_frequencies[cpu_freq_select];
  72. }
  73. enum { A375_CPU_TO_DDR, A375_CPU_TO_L2 };
  74. static const struct coreclk_ratio armada_375_coreclk_ratios[] __initconst = {
  75. { .id = A375_CPU_TO_L2, .name = "l2clk" },
  76. { .id = A375_CPU_TO_DDR, .name = "ddrclk" },
  77. };
  78. static const int armada_375_cpu_l2_ratios[32][2] __initconst = {
  79. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  80. {0, 1}, {0, 1}, {1, 2}, {0, 1},
  81. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  82. {0, 1}, {0, 1}, {0, 1}, {1, 2},
  83. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  84. {0, 1}, {1, 2}, {0, 1}, {0, 1},
  85. {0, 1}, {1, 2}, {0, 1}, {0, 1},
  86. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  87. };
  88. static const int armada_375_cpu_ddr_ratios[32][2] __initconst = {
  89. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  90. {0, 1}, {0, 1}, {1, 1}, {0, 1},
  91. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  92. {0, 1}, {0, 1}, {0, 1}, {2, 3},
  93. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  94. {0, 1}, {2, 3}, {0, 1}, {0, 1},
  95. {0, 1}, {1, 2}, {0, 1}, {0, 1},
  96. {0, 1}, {0, 1}, {0, 1}, {0, 1},
  97. };
  98. static void __init armada_375_get_clk_ratio(
  99. void __iomem *sar, int id, int *mult, int *div)
  100. {
  101. u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) &
  102. SAR1_A375_CPU_DDR_L2_FREQ_OPT_MASK);
  103. switch (id) {
  104. case A375_CPU_TO_L2:
  105. *mult = armada_375_cpu_l2_ratios[opt][0];
  106. *div = armada_375_cpu_l2_ratios[opt][1];
  107. break;
  108. case A375_CPU_TO_DDR:
  109. *mult = armada_375_cpu_ddr_ratios[opt][0];
  110. *div = armada_375_cpu_ddr_ratios[opt][1];
  111. break;
  112. }
  113. }
  114. static const struct coreclk_soc_desc armada_375_coreclks = {
  115. .get_tclk_freq = armada_375_get_tclk_freq,
  116. .get_cpu_freq = armada_375_get_cpu_freq,
  117. .get_clk_ratio = armada_375_get_clk_ratio,
  118. .ratios = armada_375_coreclk_ratios,
  119. .num_ratios = ARRAY_SIZE(armada_375_coreclk_ratios),
  120. };
  121. static void __init armada_375_coreclk_init(struct device_node *np)
  122. {
  123. mvebu_coreclk_setup(np, &armada_375_coreclks);
  124. }
  125. CLK_OF_DECLARE(armada_375_core_clk, "marvell,armada-375-core-clock",
  126. armada_375_coreclk_init);
  127. /*
  128. * Clock Gating Control
  129. */
  130. static const struct clk_gating_soc_desc armada_375_gating_desc[] __initconst = {
  131. { "mu", NULL, 2 },
  132. { "pp", NULL, 3 },
  133. { "ptp", NULL, 4 },
  134. { "pex0", NULL, 5 },
  135. { "pex1", NULL, 6 },
  136. { "audio", NULL, 8 },
  137. { "nd_clk", "nand", 11 },
  138. { "sata0_link", "sata0_core", 14 },
  139. { "sata0_core", NULL, 15 },
  140. { "usb3", NULL, 16 },
  141. { "sdio", NULL, 17 },
  142. { "usb", NULL, 18 },
  143. { "gop", NULL, 19 },
  144. { "sata1_link", "sata1_core", 20 },
  145. { "sata1_core", NULL, 21 },
  146. { "xor0", NULL, 22 },
  147. { "xor1", NULL, 23 },
  148. { "copro", NULL, 24 },
  149. { "tdm", NULL, 25 },
  150. { "crypto0_enc", NULL, 28 },
  151. { "crypto0_core", NULL, 29 },
  152. { "crypto1_enc", NULL, 30 },
  153. { "crypto1_core", NULL, 31 },
  154. { }
  155. };
  156. static void __init armada_375_clk_gating_init(struct device_node *np)
  157. {
  158. mvebu_clk_gating_setup(np, armada_375_gating_desc);
  159. }
  160. CLK_OF_DECLARE(armada_375_clk_gating, "marvell,armada-375-gating-clock",
  161. armada_375_clk_gating_init);