ap806-system-controller.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Marvell Armada AP806 System Controller
  4. *
  5. * Copyright (C) 2016 Marvell
  6. *
  7. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  8. *
  9. */
  10. #define pr_fmt(fmt) "ap806-system-controller: " fmt
  11. #include "armada_ap_cp_helper.h"
  12. #include <linux/clk-provider.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/init.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regmap.h>
  18. #define AP806_SAR_REG 0x400
  19. #define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
  20. #define AP806_CLK_NUM 6
  21. static struct clk *ap806_clks[AP806_CLK_NUM];
  22. static struct clk_onecell_data ap806_clk_data = {
  23. .clks = ap806_clks,
  24. .clk_num = AP806_CLK_NUM,
  25. };
  26. static int ap806_get_sar_clocks(unsigned int freq_mode,
  27. unsigned int *cpuclk_freq,
  28. unsigned int *dclk_freq)
  29. {
  30. switch (freq_mode) {
  31. case 0x0:
  32. *cpuclk_freq = 2000;
  33. *dclk_freq = 600;
  34. break;
  35. case 0x1:
  36. *cpuclk_freq = 2000;
  37. *dclk_freq = 525;
  38. break;
  39. case 0x6:
  40. *cpuclk_freq = 1800;
  41. *dclk_freq = 600;
  42. break;
  43. case 0x7:
  44. *cpuclk_freq = 1800;
  45. *dclk_freq = 525;
  46. break;
  47. case 0x4:
  48. *cpuclk_freq = 1600;
  49. *dclk_freq = 400;
  50. break;
  51. case 0xB:
  52. *cpuclk_freq = 1600;
  53. *dclk_freq = 450;
  54. break;
  55. case 0xD:
  56. *cpuclk_freq = 1600;
  57. *dclk_freq = 525;
  58. break;
  59. case 0x1a:
  60. *cpuclk_freq = 1400;
  61. *dclk_freq = 400;
  62. break;
  63. case 0x14:
  64. *cpuclk_freq = 1300;
  65. *dclk_freq = 400;
  66. break;
  67. case 0x17:
  68. *cpuclk_freq = 1300;
  69. *dclk_freq = 325;
  70. break;
  71. case 0x19:
  72. *cpuclk_freq = 1200;
  73. *dclk_freq = 400;
  74. break;
  75. case 0x13:
  76. *cpuclk_freq = 1000;
  77. *dclk_freq = 325;
  78. break;
  79. case 0x1d:
  80. *cpuclk_freq = 1000;
  81. *dclk_freq = 400;
  82. break;
  83. case 0x1c:
  84. *cpuclk_freq = 800;
  85. *dclk_freq = 400;
  86. break;
  87. case 0x1b:
  88. *cpuclk_freq = 600;
  89. *dclk_freq = 400;
  90. break;
  91. default:
  92. return -EINVAL;
  93. }
  94. return 0;
  95. }
  96. static int ap807_get_sar_clocks(unsigned int freq_mode,
  97. unsigned int *cpuclk_freq,
  98. unsigned int *dclk_freq)
  99. {
  100. switch (freq_mode) {
  101. case 0x0:
  102. *cpuclk_freq = 2000;
  103. *dclk_freq = 1200;
  104. break;
  105. case 0x6:
  106. *cpuclk_freq = 2200;
  107. *dclk_freq = 1200;
  108. break;
  109. case 0xD:
  110. *cpuclk_freq = 1600;
  111. *dclk_freq = 1200;
  112. break;
  113. default:
  114. return -EINVAL;
  115. }
  116. return 0;
  117. }
  118. static int ap806_syscon_common_probe(struct platform_device *pdev,
  119. struct device_node *syscon_node)
  120. {
  121. unsigned int freq_mode, cpuclk_freq, dclk_freq;
  122. const char *name, *fixedclk_name;
  123. struct device *dev = &pdev->dev;
  124. struct device_node *np = dev->of_node;
  125. struct regmap *regmap;
  126. u32 reg;
  127. int ret;
  128. regmap = syscon_node_to_regmap(syscon_node);
  129. if (IS_ERR(regmap)) {
  130. dev_err(dev, "cannot get regmap\n");
  131. return PTR_ERR(regmap);
  132. }
  133. ret = regmap_read(regmap, AP806_SAR_REG, &reg);
  134. if (ret) {
  135. dev_err(dev, "cannot read from regmap\n");
  136. return ret;
  137. }
  138. freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
  139. if (of_device_is_compatible(pdev->dev.of_node,
  140. "marvell,ap806-clock")) {
  141. ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
  142. } else if (of_device_is_compatible(pdev->dev.of_node,
  143. "marvell,ap807-clock")) {
  144. ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
  145. } else {
  146. dev_err(dev, "compatible not supported\n");
  147. return -EINVAL;
  148. }
  149. if (ret) {
  150. dev_err(dev, "invalid Sample at Reset value\n");
  151. return ret;
  152. }
  153. /* Convert to hertz */
  154. cpuclk_freq *= 1000 * 1000;
  155. dclk_freq *= 1000 * 1000;
  156. /* CPU clocks depend on the Sample At Reset configuration */
  157. name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
  158. ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
  159. 0, cpuclk_freq);
  160. if (IS_ERR(ap806_clks[0])) {
  161. ret = PTR_ERR(ap806_clks[0]);
  162. goto fail0;
  163. }
  164. name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
  165. ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
  166. cpuclk_freq);
  167. if (IS_ERR(ap806_clks[1])) {
  168. ret = PTR_ERR(ap806_clks[1]);
  169. goto fail1;
  170. }
  171. /* Fixed clock is always 1200 Mhz */
  172. fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
  173. ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
  174. 0, 1200 * 1000 * 1000);
  175. if (IS_ERR(ap806_clks[2])) {
  176. ret = PTR_ERR(ap806_clks[2]);
  177. goto fail2;
  178. }
  179. /* MSS Clock is fixed clock divided by 6 */
  180. name = ap_cp_unique_name(dev, syscon_node, "mss");
  181. ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
  182. 0, 1, 6);
  183. if (IS_ERR(ap806_clks[3])) {
  184. ret = PTR_ERR(ap806_clks[3]);
  185. goto fail3;
  186. }
  187. /* SDIO(/eMMC) Clock is fixed clock divided by 3 */
  188. name = ap_cp_unique_name(dev, syscon_node, "sdio");
  189. ap806_clks[4] = clk_register_fixed_factor(NULL, name,
  190. fixedclk_name,
  191. 0, 1, 3);
  192. if (IS_ERR(ap806_clks[4])) {
  193. ret = PTR_ERR(ap806_clks[4]);
  194. goto fail4;
  195. }
  196. /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
  197. name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
  198. ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
  199. if (IS_ERR(ap806_clks[5])) {
  200. ret = PTR_ERR(ap806_clks[5]);
  201. goto fail5;
  202. }
  203. ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
  204. if (ret)
  205. goto fail_clk_add;
  206. return 0;
  207. fail_clk_add:
  208. clk_unregister_fixed_factor(ap806_clks[5]);
  209. fail5:
  210. clk_unregister_fixed_factor(ap806_clks[4]);
  211. fail4:
  212. clk_unregister_fixed_factor(ap806_clks[3]);
  213. fail3:
  214. clk_unregister_fixed_rate(ap806_clks[2]);
  215. fail2:
  216. clk_unregister_fixed_rate(ap806_clks[1]);
  217. fail1:
  218. clk_unregister_fixed_rate(ap806_clks[0]);
  219. fail0:
  220. return ret;
  221. }
  222. static int ap806_syscon_legacy_probe(struct platform_device *pdev)
  223. {
  224. dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
  225. dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
  226. dev_warn(&pdev->dev, FW_WARN
  227. "This binding won't be supported in future kernel\n");
  228. return ap806_syscon_common_probe(pdev, pdev->dev.of_node);
  229. }
  230. static int ap806_clock_probe(struct platform_device *pdev)
  231. {
  232. return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
  233. }
  234. static const struct of_device_id ap806_syscon_legacy_of_match[] = {
  235. { .compatible = "marvell,ap806-system-controller", },
  236. { }
  237. };
  238. static struct platform_driver ap806_syscon_legacy_driver = {
  239. .probe = ap806_syscon_legacy_probe,
  240. .driver = {
  241. .name = "marvell-ap806-system-controller",
  242. .of_match_table = ap806_syscon_legacy_of_match,
  243. .suppress_bind_attrs = true,
  244. },
  245. };
  246. builtin_platform_driver(ap806_syscon_legacy_driver);
  247. static const struct of_device_id ap806_clock_of_match[] = {
  248. { .compatible = "marvell,ap806-clock", },
  249. { .compatible = "marvell,ap807-clock", },
  250. { }
  251. };
  252. static struct platform_driver ap806_clock_driver = {
  253. .probe = ap806_clock_probe,
  254. .driver = {
  255. .name = "marvell-ap806-clock",
  256. .of_match_table = ap806_clock_of_match,
  257. .suppress_bind_attrs = true,
  258. },
  259. };
  260. builtin_platform_driver(ap806_clock_driver);