ap-cpu-clk.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell Armada AP CPU Clock Controller
  4. *
  5. * Copyright (C) 2018 Marvell
  6. *
  7. * Omri Itach <omrii@marvell.com>
  8. * Gregory Clement <gregory.clement@bootlin.com>
  9. */
  10. #define pr_fmt(fmt) "ap-cpu-clk: " fmt
  11. #include <linux/clk-provider.h>
  12. #include <linux/clk.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regmap.h>
  19. #include "armada_ap_cp_helper.h"
  20. #define AP806_CPU_CLUSTER0 0
  21. #define AP806_CPU_CLUSTER1 1
  22. #define AP806_CPUS_PER_CLUSTER 2
  23. #define APN806_CPU1_MASK 0x1
  24. #define APN806_CLUSTER_NUM_OFFSET 8
  25. #define APN806_CLUSTER_NUM_MASK BIT(APN806_CLUSTER_NUM_OFFSET)
  26. #define APN806_MAX_DIVIDER 32
  27. /**
  28. * struct cpu_dfs_regs: CPU DFS register mapping
  29. * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
  30. * @force_reg: request to force new ratio regardless of relation to other clocks
  31. * @ratio_reg: central request to switch ratios
  32. */
  33. struct cpu_dfs_regs {
  34. unsigned int divider_reg;
  35. unsigned int force_reg;
  36. unsigned int ratio_reg;
  37. unsigned int ratio_state_reg;
  38. unsigned int divider_mask;
  39. unsigned int cluster_offset;
  40. unsigned int force_mask;
  41. int divider_offset;
  42. int divider_ratio;
  43. int ratio_offset;
  44. int ratio_state_offset;
  45. int ratio_state_cluster_offset;
  46. };
  47. /* AP806 CPU DFS register mapping*/
  48. #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278
  49. #define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280
  50. #define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET 0x284
  51. #define AP806_CA72MP2_0_PLL_SR_REG_OFFSET 0xC94
  52. #define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14
  53. #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
  54. #define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0
  55. #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
  56. (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
  57. #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 24
  58. #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
  59. (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
  60. #define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16
  61. #define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
  62. #define AP806_CA72MP2_0_PLL_RATIO_STATE 11
  63. #define STATUS_POLL_PERIOD_US 1
  64. #define STATUS_POLL_TIMEOUT_US 1000000
  65. #define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
  66. static const struct cpu_dfs_regs ap806_dfs_regs = {
  67. .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
  68. .force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
  69. .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
  70. .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
  71. .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
  72. .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
  73. .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
  74. .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
  75. .divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
  76. .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
  77. .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
  78. .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
  79. };
  80. /* AP807 CPU DFS register mapping */
  81. #define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET 0x278
  82. #define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET 0x27c
  83. #define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET 0xc98
  84. #define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x8
  85. #define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 18
  86. #define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
  87. (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
  88. #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET 12
  89. #define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
  90. (0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
  91. #define AP807_PLL_CR_CPU_CLK_DIV_RATIO 3
  92. #define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 0
  93. #define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
  94. (0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
  95. #define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 6
  96. #define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET 20
  97. #define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET 3
  98. static const struct cpu_dfs_regs ap807_dfs_regs = {
  99. .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
  100. .force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
  101. .ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
  102. .ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
  103. .divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
  104. .cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
  105. .force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
  106. .divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
  107. .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
  108. .ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
  109. .ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
  110. .ratio_state_cluster_offset =
  111. AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
  112. };
  113. /*
  114. * struct ap806_clk: CPU cluster clock controller instance
  115. * @cluster: Cluster clock controller index
  116. * @clk_name: Cluster clock controller name
  117. * @dev : Cluster clock device
  118. * @hw: HW specific structure of Cluster clock controller
  119. * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
  120. */
  121. struct ap_cpu_clk {
  122. unsigned int cluster;
  123. const char *clk_name;
  124. struct device *dev;
  125. struct clk_hw hw;
  126. struct regmap *pll_cr_base;
  127. const struct cpu_dfs_regs *pll_regs;
  128. };
  129. static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
  130. unsigned long parent_rate)
  131. {
  132. struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
  133. unsigned int cpu_clkdiv_reg;
  134. int cpu_clkdiv_ratio;
  135. cpu_clkdiv_reg = clk->pll_regs->divider_reg +
  136. (clk->cluster * clk->pll_regs->cluster_offset);
  137. regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
  138. cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
  139. cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
  140. return parent_rate / cpu_clkdiv_ratio;
  141. }
  142. static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  143. unsigned long parent_rate)
  144. {
  145. struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
  146. int ret, reg, divider = parent_rate / rate;
  147. unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
  148. cpu_clkdiv_reg = clk->pll_regs->divider_reg +
  149. (clk->cluster * clk->pll_regs->cluster_offset);
  150. cpu_force_reg = clk->pll_regs->force_reg +
  151. (clk->cluster * clk->pll_regs->cluster_offset);
  152. cpu_ratio_reg = clk->pll_regs->ratio_reg +
  153. (clk->cluster * clk->pll_regs->cluster_offset);
  154. regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);
  155. reg &= ~(clk->pll_regs->divider_mask);
  156. reg |= (divider << clk->pll_regs->divider_offset);
  157. /*
  158. * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
  159. * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
  160. */
  161. if (clk->pll_regs->divider_ratio) {
  162. reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
  163. reg |= ((divider * clk->pll_regs->divider_ratio) <<
  164. AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
  165. }
  166. regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);
  167. regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
  168. clk->pll_regs->force_mask,
  169. clk->pll_regs->force_mask);
  170. regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
  171. BIT(clk->pll_regs->ratio_offset),
  172. BIT(clk->pll_regs->ratio_offset));
  173. stable_bit = BIT(clk->pll_regs->ratio_state_offset +
  174. clk->cluster *
  175. clk->pll_regs->ratio_state_cluster_offset);
  176. ret = regmap_read_poll_timeout(clk->pll_cr_base,
  177. clk->pll_regs->ratio_state_reg, reg,
  178. reg & stable_bit, STATUS_POLL_PERIOD_US,
  179. STATUS_POLL_TIMEOUT_US);
  180. if (ret)
  181. return ret;
  182. regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
  183. BIT(clk->pll_regs->ratio_offset), 0);
  184. return 0;
  185. }
  186. static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  187. unsigned long *parent_rate)
  188. {
  189. int divider = *parent_rate / rate;
  190. divider = min(divider, APN806_MAX_DIVIDER);
  191. return *parent_rate / divider;
  192. }
  193. static const struct clk_ops ap_cpu_clk_ops = {
  194. .recalc_rate = ap_cpu_clk_recalc_rate,
  195. .round_rate = ap_cpu_clk_round_rate,
  196. .set_rate = ap_cpu_clk_set_rate,
  197. };
  198. static int ap_cpu_clock_probe(struct platform_device *pdev)
  199. {
  200. int ret, nclusters = 0, cluster_index = 0;
  201. struct device *dev = &pdev->dev;
  202. struct device_node *dn, *np = dev->of_node;
  203. struct clk_hw_onecell_data *ap_cpu_data;
  204. struct ap_cpu_clk *ap_cpu_clk;
  205. struct regmap *regmap;
  206. regmap = syscon_node_to_regmap(np->parent);
  207. if (IS_ERR(regmap)) {
  208. pr_err("cannot get pll_cr_base regmap\n");
  209. return PTR_ERR(regmap);
  210. }
  211. /*
  212. * AP806 has 4 cpus and DFS for AP806 is controlled per
  213. * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
  214. * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
  215. * they are enabled or not. Since cpu0 is the boot cpu, then
  216. * cluster0 must exist. If cpu2 or cpu3 is enabled, cluster1
  217. * will exist and the cluster number is 2; otherwise the
  218. * cluster number is 1.
  219. */
  220. nclusters = 1;
  221. for_each_of_cpu_node(dn) {
  222. int cpu, err;
  223. err = of_property_read_u32(dn, "reg", &cpu);
  224. if (WARN_ON(err)) {
  225. of_node_put(dn);
  226. return err;
  227. }
  228. /* If cpu2 or cpu3 is enabled */
  229. if (cpu & APN806_CLUSTER_NUM_MASK) {
  230. nclusters = 2;
  231. of_node_put(dn);
  232. break;
  233. }
  234. }
  235. /*
  236. * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
  237. * so allocate structs per cluster
  238. */
  239. ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
  240. GFP_KERNEL);
  241. if (!ap_cpu_clk)
  242. return -ENOMEM;
  243. ap_cpu_data = devm_kzalloc(dev, struct_size(ap_cpu_data, hws,
  244. nclusters),
  245. GFP_KERNEL);
  246. if (!ap_cpu_data)
  247. return -ENOMEM;
  248. for_each_of_cpu_node(dn) {
  249. char *clk_name = "cpu-cluster-0";
  250. struct clk_init_data init;
  251. const char *parent_name;
  252. struct clk *parent;
  253. int cpu, err;
  254. err = of_property_read_u32(dn, "reg", &cpu);
  255. if (WARN_ON(err)) {
  256. of_node_put(dn);
  257. return err;
  258. }
  259. cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
  260. cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
  261. /* Initialize once for one cluster */
  262. if (ap_cpu_data->hws[cluster_index])
  263. continue;
  264. parent = of_clk_get(np, cluster_index);
  265. if (IS_ERR(parent)) {
  266. dev_err(dev, "Could not get the clock parent\n");
  267. of_node_put(dn);
  268. return -EINVAL;
  269. }
  270. parent_name = __clk_get_name(parent);
  271. clk_name[12] += cluster_index;
  272. ap_cpu_clk[cluster_index].clk_name =
  273. ap_cp_unique_name(dev, np->parent, clk_name);
  274. ap_cpu_clk[cluster_index].cluster = cluster_index;
  275. ap_cpu_clk[cluster_index].pll_cr_base = regmap;
  276. ap_cpu_clk[cluster_index].hw.init = &init;
  277. ap_cpu_clk[cluster_index].dev = dev;
  278. ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
  279. init.name = ap_cpu_clk[cluster_index].clk_name;
  280. init.ops = &ap_cpu_clk_ops;
  281. init.num_parents = 1;
  282. init.parent_names = &parent_name;
  283. ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
  284. if (ret) {
  285. of_node_put(dn);
  286. return ret;
  287. }
  288. ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
  289. }
  290. ap_cpu_data->num = cluster_index + 1;
  291. ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
  292. if (ret)
  293. dev_err(dev, "failed to register OF clock provider\n");
  294. return ret;
  295. }
  296. static const struct of_device_id ap_cpu_clock_of_match[] = {
  297. {
  298. .compatible = "marvell,ap806-cpu-clock",
  299. .data = &ap806_dfs_regs,
  300. },
  301. {
  302. .compatible = "marvell,ap807-cpu-clock",
  303. .data = &ap807_dfs_regs,
  304. },
  305. { }
  306. };
  307. static struct platform_driver ap_cpu_clock_driver = {
  308. .probe = ap_cpu_clock_probe,
  309. .driver = {
  310. .name = "marvell-ap-cpu-clock",
  311. .of_match_table = ap_cpu_clock_of_match,
  312. .suppress_bind_attrs = true,
  313. },
  314. };
  315. builtin_platform_driver(ap_cpu_clock_driver);