clk-pxa168.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357
  1. /*
  2. * pxa168 clock framework source file
  3. *
  4. * Copyright (C) 2012 Marvell
  5. * Chao Xie <xiechao.mail@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk/mmp.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/err.h>
  19. #include "clk.h"
  20. #define APBC_RTC 0x28
  21. #define APBC_TWSI0 0x2c
  22. #define APBC_KPC 0x30
  23. #define APBC_UART0 0x0
  24. #define APBC_UART1 0x4
  25. #define APBC_GPIO 0x8
  26. #define APBC_PWM0 0xc
  27. #define APBC_PWM1 0x10
  28. #define APBC_PWM2 0x14
  29. #define APBC_PWM3 0x18
  30. #define APBC_SSP0 0x81c
  31. #define APBC_SSP1 0x820
  32. #define APBC_SSP2 0x84c
  33. #define APBC_SSP3 0x858
  34. #define APBC_SSP4 0x85c
  35. #define APBC_TWSI1 0x6c
  36. #define APBC_UART2 0x70
  37. #define APMU_SDH0 0x54
  38. #define APMU_SDH1 0x58
  39. #define APMU_USB 0x5c
  40. #define APMU_DISP0 0x4c
  41. #define APMU_CCIC0 0x50
  42. #define APMU_DFC 0x60
  43. #define MPMU_UART_PLL 0x14
  44. static DEFINE_SPINLOCK(clk_lock);
  45. static struct mmp_clk_factor_masks uart_factor_masks = {
  46. .factor = 2,
  47. .num_mask = 0x1fff,
  48. .den_mask = 0x1fff,
  49. .num_shift = 16,
  50. .den_shift = 0,
  51. };
  52. static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  53. {.num = 8125, .den = 1536}, /*14.745MHZ */
  54. };
  55. static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
  56. static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
  57. static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
  58. static const char *disp_parent[] = {"pll1_2", "pll1_12"};
  59. static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
  60. static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
  61. void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
  62. phys_addr_t apbc_phys)
  63. {
  64. struct clk *clk;
  65. struct clk *uart_pll;
  66. void __iomem *mpmu_base;
  67. void __iomem *apmu_base;
  68. void __iomem *apbc_base;
  69. mpmu_base = ioremap(mpmu_phys, SZ_4K);
  70. if (!mpmu_base) {
  71. pr_err("error to ioremap MPMU base\n");
  72. return;
  73. }
  74. apmu_base = ioremap(apmu_phys, SZ_4K);
  75. if (!apmu_base) {
  76. pr_err("error to ioremap APMU base\n");
  77. return;
  78. }
  79. apbc_base = ioremap(apbc_phys, SZ_4K);
  80. if (!apbc_base) {
  81. pr_err("error to ioremap APBC base\n");
  82. return;
  83. }
  84. clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
  85. clk_register_clkdev(clk, "clk32", NULL);
  86. clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
  87. clk_register_clkdev(clk, "vctcxo", NULL);
  88. clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
  89. clk_register_clkdev(clk, "pll1", NULL);
  90. clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
  91. CLK_SET_RATE_PARENT, 1, 2);
  92. clk_register_clkdev(clk, "pll1_2", NULL);
  93. clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
  94. CLK_SET_RATE_PARENT, 1, 2);
  95. clk_register_clkdev(clk, "pll1_4", NULL);
  96. clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
  97. CLK_SET_RATE_PARENT, 1, 2);
  98. clk_register_clkdev(clk, "pll1_8", NULL);
  99. clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
  100. CLK_SET_RATE_PARENT, 1, 2);
  101. clk_register_clkdev(clk, "pll1_16", NULL);
  102. clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
  103. CLK_SET_RATE_PARENT, 1, 3);
  104. clk_register_clkdev(clk, "pll1_6", NULL);
  105. clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
  106. CLK_SET_RATE_PARENT, 1, 2);
  107. clk_register_clkdev(clk, "pll1_12", NULL);
  108. clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
  109. CLK_SET_RATE_PARENT, 1, 2);
  110. clk_register_clkdev(clk, "pll1_24", NULL);
  111. clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
  112. CLK_SET_RATE_PARENT, 1, 2);
  113. clk_register_clkdev(clk, "pll1_48", NULL);
  114. clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
  115. CLK_SET_RATE_PARENT, 1, 2);
  116. clk_register_clkdev(clk, "pll1_96", NULL);
  117. clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
  118. CLK_SET_RATE_PARENT, 1, 13);
  119. clk_register_clkdev(clk, "pll1_13", NULL);
  120. clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
  121. CLK_SET_RATE_PARENT, 2, 3);
  122. clk_register_clkdev(clk, "pll1_13_1_5", NULL);
  123. clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
  124. CLK_SET_RATE_PARENT, 2, 3);
  125. clk_register_clkdev(clk, "pll1_2_1_5", NULL);
  126. clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
  127. CLK_SET_RATE_PARENT, 3, 16);
  128. clk_register_clkdev(clk, "pll1_3_16", NULL);
  129. uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
  130. mpmu_base + MPMU_UART_PLL,
  131. &uart_factor_masks, uart_factor_tbl,
  132. ARRAY_SIZE(uart_factor_tbl), &clk_lock);
  133. clk_set_rate(uart_pll, 14745600);
  134. clk_register_clkdev(uart_pll, "uart_pll", NULL);
  135. clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
  136. apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
  137. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
  138. clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
  139. apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
  140. clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
  141. clk = mmp_clk_register_apbc("gpio", "vctcxo",
  142. apbc_base + APBC_GPIO, 10, 0, &clk_lock);
  143. clk_register_clkdev(clk, NULL, "mmp-gpio");
  144. clk = mmp_clk_register_apbc("kpc", "clk32",
  145. apbc_base + APBC_KPC, 10, 0, &clk_lock);
  146. clk_register_clkdev(clk, NULL, "pxa27x-keypad");
  147. clk = mmp_clk_register_apbc("rtc", "clk32",
  148. apbc_base + APBC_RTC, 10, 0, &clk_lock);
  149. clk_register_clkdev(clk, NULL, "sa1100-rtc");
  150. clk = mmp_clk_register_apbc("pwm0", "pll1_48",
  151. apbc_base + APBC_PWM0, 10, 0, &clk_lock);
  152. clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
  153. clk = mmp_clk_register_apbc("pwm1", "pll1_48",
  154. apbc_base + APBC_PWM1, 10, 0, &clk_lock);
  155. clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
  156. clk = mmp_clk_register_apbc("pwm2", "pll1_48",
  157. apbc_base + APBC_PWM2, 10, 0, &clk_lock);
  158. clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
  159. clk = mmp_clk_register_apbc("pwm3", "pll1_48",
  160. apbc_base + APBC_PWM3, 10, 0, &clk_lock);
  161. clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
  162. clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
  163. ARRAY_SIZE(uart_parent),
  164. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  165. apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
  166. clk_set_parent(clk, uart_pll);
  167. clk_register_clkdev(clk, "uart_mux.0", NULL);
  168. clk = mmp_clk_register_apbc("uart0", "uart0_mux",
  169. apbc_base + APBC_UART0, 10, 0, &clk_lock);
  170. clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
  171. clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
  172. ARRAY_SIZE(uart_parent),
  173. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  174. apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
  175. clk_set_parent(clk, uart_pll);
  176. clk_register_clkdev(clk, "uart_mux.1", NULL);
  177. clk = mmp_clk_register_apbc("uart1", "uart1_mux",
  178. apbc_base + APBC_UART1, 10, 0, &clk_lock);
  179. clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
  180. clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
  181. ARRAY_SIZE(uart_parent),
  182. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  183. apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
  184. clk_set_parent(clk, uart_pll);
  185. clk_register_clkdev(clk, "uart_mux.2", NULL);
  186. clk = mmp_clk_register_apbc("uart2", "uart2_mux",
  187. apbc_base + APBC_UART2, 10, 0, &clk_lock);
  188. clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
  189. clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
  190. ARRAY_SIZE(ssp_parent),
  191. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  192. apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
  193. clk_register_clkdev(clk, "uart_mux.0", NULL);
  194. clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
  195. 10, 0, &clk_lock);
  196. clk_register_clkdev(clk, NULL, "mmp-ssp.0");
  197. clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
  198. ARRAY_SIZE(ssp_parent),
  199. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  200. apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
  201. clk_register_clkdev(clk, "ssp_mux.1", NULL);
  202. clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
  203. 10, 0, &clk_lock);
  204. clk_register_clkdev(clk, NULL, "mmp-ssp.1");
  205. clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
  206. ARRAY_SIZE(ssp_parent),
  207. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  208. apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
  209. clk_register_clkdev(clk, "ssp_mux.2", NULL);
  210. clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
  211. 10, 0, &clk_lock);
  212. clk_register_clkdev(clk, NULL, "mmp-ssp.2");
  213. clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
  214. ARRAY_SIZE(ssp_parent),
  215. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  216. apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
  217. clk_register_clkdev(clk, "ssp_mux.3", NULL);
  218. clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
  219. 10, 0, &clk_lock);
  220. clk_register_clkdev(clk, NULL, "mmp-ssp.3");
  221. clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
  222. ARRAY_SIZE(ssp_parent),
  223. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  224. apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
  225. clk_register_clkdev(clk, "ssp_mux.4", NULL);
  226. clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
  227. 10, 0, &clk_lock);
  228. clk_register_clkdev(clk, NULL, "mmp-ssp.4");
  229. clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
  230. 0x19b, &clk_lock);
  231. clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
  232. clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
  233. ARRAY_SIZE(sdh_parent),
  234. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  235. apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
  236. clk_register_clkdev(clk, "sdh0_mux", NULL);
  237. clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
  238. 0x1b, &clk_lock);
  239. clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
  240. clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
  241. ARRAY_SIZE(sdh_parent),
  242. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  243. apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
  244. clk_register_clkdev(clk, "sdh1_mux", NULL);
  245. clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
  246. 0x1b, &clk_lock);
  247. clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
  248. clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
  249. 0x9, &clk_lock);
  250. clk_register_clkdev(clk, "usb_clk", NULL);
  251. clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
  252. 0x12, &clk_lock);
  253. clk_register_clkdev(clk, "sph_clk", NULL);
  254. clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
  255. ARRAY_SIZE(disp_parent),
  256. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  257. apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
  258. clk_register_clkdev(clk, "disp_mux.0", NULL);
  259. clk = mmp_clk_register_apmu("disp0", "disp0_mux",
  260. apmu_base + APMU_DISP0, 0x1b, &clk_lock);
  261. clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
  262. clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
  263. apmu_base + APMU_DISP0, 0x24, &clk_lock);
  264. clk_register_clkdev(clk, "hclk", "mmp-disp.0");
  265. clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
  266. ARRAY_SIZE(ccic_parent),
  267. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  268. apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
  269. clk_register_clkdev(clk, "ccic_mux.0", NULL);
  270. clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
  271. apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
  272. clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
  273. clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
  274. ARRAY_SIZE(ccic_phy_parent),
  275. CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
  276. apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
  277. clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
  278. clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
  279. apmu_base + APMU_CCIC0, 0x24, &clk_lock);
  280. clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
  281. clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
  282. CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
  283. 10, 5, 0, &clk_lock);
  284. clk_register_clkdev(clk, "sphyclk_div", NULL);
  285. clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
  286. apmu_base + APMU_CCIC0, 0x300, &clk_lock);
  287. clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
  288. }