clk-apbc.c 3.3 KB

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  1. /*
  2. * mmp APB clock operation source file
  3. *
  4. * Copyright (C) 2012 Marvell
  5. * Chao Xie <xiechao.mail@gmail.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/io.h>
  13. #include <linux/err.h>
  14. #include <linux/delay.h>
  15. #include <linux/slab.h>
  16. #include "clk.h"
  17. /* Common APB clock register bit definitions */
  18. #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
  19. #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
  20. #define APBC_RST (1 << 2) /* Reset Generation */
  21. #define APBC_POWER (1 << 7) /* Reset Generation */
  22. #define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
  23. struct clk_apbc {
  24. struct clk_hw hw;
  25. void __iomem *base;
  26. unsigned int delay;
  27. unsigned int flags;
  28. spinlock_t *lock;
  29. };
  30. static int clk_apbc_prepare(struct clk_hw *hw)
  31. {
  32. struct clk_apbc *apbc = to_clk_apbc(hw);
  33. unsigned int data;
  34. unsigned long flags = 0;
  35. /*
  36. * It may share same register as MUX clock,
  37. * and it will impact FNCLK enable. Spinlock is needed
  38. */
  39. if (apbc->lock)
  40. spin_lock_irqsave(apbc->lock, flags);
  41. data = readl_relaxed(apbc->base);
  42. if (apbc->flags & APBC_POWER_CTRL)
  43. data |= APBC_POWER;
  44. data |= APBC_FNCLK;
  45. writel_relaxed(data, apbc->base);
  46. if (apbc->lock)
  47. spin_unlock_irqrestore(apbc->lock, flags);
  48. udelay(apbc->delay);
  49. if (apbc->lock)
  50. spin_lock_irqsave(apbc->lock, flags);
  51. data = readl_relaxed(apbc->base);
  52. data |= APBC_APBCLK;
  53. writel_relaxed(data, apbc->base);
  54. if (apbc->lock)
  55. spin_unlock_irqrestore(apbc->lock, flags);
  56. udelay(apbc->delay);
  57. if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
  58. if (apbc->lock)
  59. spin_lock_irqsave(apbc->lock, flags);
  60. data = readl_relaxed(apbc->base);
  61. data &= ~APBC_RST;
  62. writel_relaxed(data, apbc->base);
  63. if (apbc->lock)
  64. spin_unlock_irqrestore(apbc->lock, flags);
  65. }
  66. return 0;
  67. }
  68. static void clk_apbc_unprepare(struct clk_hw *hw)
  69. {
  70. struct clk_apbc *apbc = to_clk_apbc(hw);
  71. unsigned long data;
  72. unsigned long flags = 0;
  73. if (apbc->lock)
  74. spin_lock_irqsave(apbc->lock, flags);
  75. data = readl_relaxed(apbc->base);
  76. if (apbc->flags & APBC_POWER_CTRL)
  77. data &= ~APBC_POWER;
  78. data &= ~APBC_FNCLK;
  79. writel_relaxed(data, apbc->base);
  80. if (apbc->lock)
  81. spin_unlock_irqrestore(apbc->lock, flags);
  82. udelay(10);
  83. if (apbc->lock)
  84. spin_lock_irqsave(apbc->lock, flags);
  85. data = readl_relaxed(apbc->base);
  86. data &= ~APBC_APBCLK;
  87. writel_relaxed(data, apbc->base);
  88. if (apbc->lock)
  89. spin_unlock_irqrestore(apbc->lock, flags);
  90. }
  91. static const struct clk_ops clk_apbc_ops = {
  92. .prepare = clk_apbc_prepare,
  93. .unprepare = clk_apbc_unprepare,
  94. };
  95. struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
  96. void __iomem *base, unsigned int delay,
  97. unsigned int apbc_flags, spinlock_t *lock)
  98. {
  99. struct clk_apbc *apbc;
  100. struct clk *clk;
  101. struct clk_init_data init;
  102. apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
  103. if (!apbc)
  104. return NULL;
  105. init.name = name;
  106. init.ops = &clk_apbc_ops;
  107. init.flags = CLK_SET_RATE_PARENT;
  108. init.parent_names = (parent_name ? &parent_name : NULL);
  109. init.num_parents = (parent_name ? 1 : 0);
  110. apbc->base = base;
  111. apbc->delay = delay;
  112. apbc->flags = apbc_flags;
  113. apbc->lock = lock;
  114. apbc->hw.init = &init;
  115. clk = clk_register(NULL, &apbc->hw);
  116. if (IS_ERR(clk))
  117. kfree(apbc);
  118. return clk;
  119. }