clk-pic32mzda.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Purna Chandra Mandal,<purna.mandal@microchip.com>
  4. * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
  5. */
  6. #include <dt-bindings/clock/microchip,pic32-clock.h>
  7. #include <linux/clk.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/clkdev.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <asm/traps.h>
  16. #include "clk-core.h"
  17. /* FRC Postscaler */
  18. #define OSC_FRCDIV_MASK 0x07
  19. #define OSC_FRCDIV_SHIFT 24
  20. /* SPLL fields */
  21. #define PLL_ICLK_MASK 0x01
  22. #define PLL_ICLK_SHIFT 7
  23. #define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags) \
  24. { \
  25. .ctrl_reg = (__reg), \
  26. .init_data = { \
  27. .name = (__clk_name), \
  28. .parent_names = (const char *[]) { \
  29. "sys_clk" \
  30. }, \
  31. .num_parents = 1, \
  32. .ops = &pic32_pbclk_ops, \
  33. .flags = (__flags), \
  34. }, \
  35. }
  36. #define DECLARE_REFO_CLOCK(__clkid, __reg) \
  37. { \
  38. .ctrl_reg = (__reg), \
  39. .init_data = { \
  40. .name = "refo" #__clkid "_clk", \
  41. .parent_names = (const char *[]) { \
  42. "sys_clk", "pb1_clk", "posc_clk", \
  43. "frc_clk", "lprc_clk", "sosc_clk", \
  44. "sys_pll", "refi" #__clkid "_clk", \
  45. "bfrc_clk", \
  46. }, \
  47. .num_parents = 9, \
  48. .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
  49. .ops = &pic32_roclk_ops, \
  50. }, \
  51. .parent_map = (const u32[]) { \
  52. 0, 1, 2, 3, 4, 5, 7, 8, 9 \
  53. }, \
  54. }
  55. static const struct pic32_ref_osc_data ref_clks[] = {
  56. DECLARE_REFO_CLOCK(1, 0x80),
  57. DECLARE_REFO_CLOCK(2, 0xa0),
  58. DECLARE_REFO_CLOCK(3, 0xc0),
  59. DECLARE_REFO_CLOCK(4, 0xe0),
  60. DECLARE_REFO_CLOCK(5, 0x100),
  61. };
  62. static const struct pic32_periph_clk_data periph_clocks[] = {
  63. DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0),
  64. DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED),
  65. DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0),
  66. DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0),
  67. DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0),
  68. DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0),
  69. DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED),
  70. };
  71. static const struct pic32_sys_clk_data sys_mux_clk = {
  72. .slew_reg = 0x1c0,
  73. .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
  74. .init_data = {
  75. .name = "sys_clk",
  76. .parent_names = (const char *[]) {
  77. "frcdiv_clk", "sys_pll", "posc_clk",
  78. "sosc_clk", "lprc_clk", "frcdiv_clk",
  79. },
  80. .num_parents = 6,
  81. .ops = &pic32_sclk_ops,
  82. },
  83. .parent_map = (const u32[]) {
  84. 0, 1, 2, 4, 5, 7,
  85. },
  86. };
  87. static const struct pic32_sys_pll_data sys_pll = {
  88. .ctrl_reg = 0x020,
  89. .status_reg = 0x1d0,
  90. .lock_mask = BIT(7),
  91. .init_data = {
  92. .name = "sys_pll",
  93. .parent_names = (const char *[]) {
  94. "spll_mux_clk"
  95. },
  96. .num_parents = 1,
  97. .ops = &pic32_spll_ops,
  98. },
  99. };
  100. static const struct pic32_sec_osc_data sosc_clk = {
  101. .status_reg = 0x1d0,
  102. .enable_mask = BIT(1),
  103. .status_mask = BIT(4),
  104. .fixed_rate = 32768,
  105. .init_data = {
  106. .name = "sosc_clk",
  107. .parent_names = NULL,
  108. .ops = &pic32_sosc_ops,
  109. },
  110. };
  111. static int pic32mzda_critical_clks[] = {
  112. PB2CLK, PB7CLK
  113. };
  114. /* PIC32MZDA clock data */
  115. struct pic32mzda_clk_data {
  116. struct clk *clks[MAXCLKS];
  117. struct pic32_clk_common core;
  118. struct clk_onecell_data onecell_data;
  119. struct notifier_block failsafe_notifier;
  120. };
  121. static int pic32_fscm_nmi(struct notifier_block *nb,
  122. unsigned long action, void *data)
  123. {
  124. struct pic32mzda_clk_data *cd;
  125. cd = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier);
  126. /* SYSCLK is now running from BFRCCLK. Report clock failure. */
  127. if (readl(cd->core.iobase) & BIT(2))
  128. pr_alert("pic32-clk: FSCM detected clk failure.\n");
  129. /* TODO: detect reason of failure and recover accordingly */
  130. return NOTIFY_OK;
  131. }
  132. static int pic32mzda_clk_probe(struct platform_device *pdev)
  133. {
  134. const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"};
  135. struct device_node *np = pdev->dev.of_node;
  136. struct pic32mzda_clk_data *cd;
  137. struct pic32_clk_common *core;
  138. struct clk *pll_mux_clk, *clk;
  139. struct clk **clks;
  140. int nr_clks, i, ret;
  141. cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);
  142. if (!cd)
  143. return -ENOMEM;
  144. core = &cd->core;
  145. core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));
  146. if (IS_ERR(core->iobase)) {
  147. dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");
  148. return PTR_ERR(core->iobase);
  149. }
  150. spin_lock_init(&core->reg_lock);
  151. core->dev = &pdev->dev;
  152. clks = &cd->clks[0];
  153. /* register fixed rate clocks */
  154. clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
  155. 0, 24000000);
  156. clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
  157. 0, 8000000);
  158. clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
  159. 0, 8000000);
  160. clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
  161. 0, 32000);
  162. clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
  163. 0, 24000000);
  164. /* fixed rate (optional) clock */
  165. if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
  166. pr_info("pic32-clk: dt requests SOSC.\n");
  167. clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);
  168. }
  169. /* divider clock */
  170. clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
  171. "frc_clk", 0,
  172. core->iobase,
  173. OSC_FRCDIV_SHIFT,
  174. OSC_FRCDIV_MASK,
  175. CLK_DIVIDER_POWER_OF_TWO,
  176. &core->reg_lock);
  177. /* PLL ICLK mux */
  178. pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
  179. pll_mux_parents, 2, 0,
  180. core->iobase + 0x020,
  181. PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);
  182. if (IS_ERR(pll_mux_clk))
  183. pr_err("spll_mux_clk: clk register failed\n");
  184. /* PLL */
  185. clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);
  186. /* SYSTEM clock */
  187. clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);
  188. /* Peripheral bus clocks */
  189. for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++)
  190. clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i],
  191. core);
  192. /* Reference oscillator clock */
  193. for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++)
  194. clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);
  195. /* register clkdev */
  196. for (i = 0; i < MAXCLKS; i++) {
  197. if (IS_ERR(clks[i]))
  198. continue;
  199. clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i]));
  200. }
  201. /* register clock provider */
  202. cd->onecell_data.clks = clks;
  203. cd->onecell_data.clk_num = MAXCLKS;
  204. ret = of_clk_add_provider(np, of_clk_src_onecell_get,
  205. &cd->onecell_data);
  206. if (ret)
  207. return ret;
  208. /* force enable critical clocks */
  209. for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) {
  210. clk = clks[pic32mzda_critical_clks[i]];
  211. if (clk_prepare_enable(clk))
  212. dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",
  213. __clk_get_name(clk));
  214. }
  215. /* register NMI for failsafe clock monitor */
  216. cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;
  217. return register_nmi_notifier(&cd->failsafe_notifier);
  218. }
  219. static const struct of_device_id pic32mzda_clk_match_table[] = {
  220. { .compatible = "microchip,pic32mzda-clk", },
  221. { }
  222. };
  223. MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table);
  224. static struct platform_driver pic32mzda_clk_driver = {
  225. .probe = pic32mzda_clk_probe,
  226. .driver = {
  227. .name = "clk-pic32mzda",
  228. .of_match_table = pic32mzda_clk_match_table,
  229. },
  230. };
  231. static int __init microchip_pic32mzda_clk_init(void)
  232. {
  233. return platform_driver_register(&pic32mzda_clk_driver);
  234. }
  235. core_initcall(microchip_pic32mzda_clk_init);
  236. MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver");
  237. MODULE_LICENSE("GPL v2");
  238. MODULE_ALIAS("platform:clk-pic32mzda");