clk-core.c 25 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Purna Chandra Mandal,<purna.mandal@microchip.com>
  4. * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/delay.h>
  8. #include <linux/device.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/iopoll.h>
  12. #include <asm/mach-pic32/pic32.h>
  13. #include <asm/traps.h>
  14. #include "clk-core.h"
  15. /* OSCCON Reg fields */
  16. #define OSC_CUR_MASK 0x07
  17. #define OSC_CUR_SHIFT 12
  18. #define OSC_NEW_MASK 0x07
  19. #define OSC_NEW_SHIFT 8
  20. #define OSC_SWEN BIT(0)
  21. /* SPLLCON Reg fields */
  22. #define PLL_RANGE_MASK 0x07
  23. #define PLL_RANGE_SHIFT 0
  24. #define PLL_ICLK_MASK 0x01
  25. #define PLL_ICLK_SHIFT 7
  26. #define PLL_IDIV_MASK 0x07
  27. #define PLL_IDIV_SHIFT 8
  28. #define PLL_ODIV_MASK 0x07
  29. #define PLL_ODIV_SHIFT 24
  30. #define PLL_MULT_MASK 0x7F
  31. #define PLL_MULT_SHIFT 16
  32. #define PLL_MULT_MAX 128
  33. #define PLL_ODIV_MIN 1
  34. #define PLL_ODIV_MAX 5
  35. /* Peripheral Bus Clock Reg Fields */
  36. #define PB_DIV_MASK 0x7f
  37. #define PB_DIV_SHIFT 0
  38. #define PB_DIV_READY BIT(11)
  39. #define PB_DIV_ENABLE BIT(15)
  40. #define PB_DIV_MAX 128
  41. #define PB_DIV_MIN 0
  42. /* Reference Oscillator Control Reg fields */
  43. #define REFO_SEL_MASK 0x0f
  44. #define REFO_SEL_SHIFT 0
  45. #define REFO_ACTIVE BIT(8)
  46. #define REFO_DIVSW_EN BIT(9)
  47. #define REFO_OE BIT(12)
  48. #define REFO_ON BIT(15)
  49. #define REFO_DIV_SHIFT 16
  50. #define REFO_DIV_MASK 0x7fff
  51. /* Reference Oscillator Trim Register Fields */
  52. #define REFO_TRIM_REG 0x10
  53. #define REFO_TRIM_MASK 0x1ff
  54. #define REFO_TRIM_SHIFT 23
  55. #define REFO_TRIM_MAX 511
  56. /* Mux Slew Control Register fields */
  57. #define SLEW_BUSY BIT(0)
  58. #define SLEW_DOWNEN BIT(1)
  59. #define SLEW_UPEN BIT(2)
  60. #define SLEW_DIV 0x07
  61. #define SLEW_DIV_SHIFT 8
  62. #define SLEW_SYSDIV 0x0f
  63. #define SLEW_SYSDIV_SHIFT 20
  64. /* Clock Poll Timeout */
  65. #define LOCK_TIMEOUT_US USEC_PER_MSEC
  66. /* SoC specific clock needed during SPLL clock rate switch */
  67. static struct clk_hw *pic32_sclk_hw;
  68. /* add instruction pipeline delay while CPU clock is in-transition. */
  69. #define cpu_nop5() \
  70. do { \
  71. __asm__ __volatile__("nop"); \
  72. __asm__ __volatile__("nop"); \
  73. __asm__ __volatile__("nop"); \
  74. __asm__ __volatile__("nop"); \
  75. __asm__ __volatile__("nop"); \
  76. } while (0)
  77. /* Perpheral bus clocks */
  78. struct pic32_periph_clk {
  79. struct clk_hw hw;
  80. void __iomem *ctrl_reg;
  81. struct pic32_clk_common *core;
  82. };
  83. #define clkhw_to_pbclk(_hw) container_of(_hw, struct pic32_periph_clk, hw)
  84. static int pbclk_is_enabled(struct clk_hw *hw)
  85. {
  86. struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
  87. return readl(pb->ctrl_reg) & PB_DIV_ENABLE;
  88. }
  89. static int pbclk_enable(struct clk_hw *hw)
  90. {
  91. struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
  92. writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg));
  93. return 0;
  94. }
  95. static void pbclk_disable(struct clk_hw *hw)
  96. {
  97. struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
  98. writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg));
  99. }
  100. static unsigned long calc_best_divided_rate(unsigned long rate,
  101. unsigned long parent_rate,
  102. u32 divider_max,
  103. u32 divider_min)
  104. {
  105. unsigned long divided_rate, divided_rate_down, best_rate;
  106. unsigned long div, div_up;
  107. /* eq. clk_rate = parent_rate / divider.
  108. *
  109. * Find best divider to produce closest of target divided rate.
  110. */
  111. div = parent_rate / rate;
  112. div = clamp_val(div, divider_min, divider_max);
  113. div_up = clamp_val(div + 1, divider_min, divider_max);
  114. divided_rate = parent_rate / div;
  115. divided_rate_down = parent_rate / div_up;
  116. if (abs(rate - divided_rate_down) < abs(rate - divided_rate))
  117. best_rate = divided_rate_down;
  118. else
  119. best_rate = divided_rate;
  120. return best_rate;
  121. }
  122. static inline u32 pbclk_read_pbdiv(struct pic32_periph_clk *pb)
  123. {
  124. return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1;
  125. }
  126. static unsigned long pbclk_recalc_rate(struct clk_hw *hw,
  127. unsigned long parent_rate)
  128. {
  129. struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
  130. return parent_rate / pbclk_read_pbdiv(pb);
  131. }
  132. static long pbclk_round_rate(struct clk_hw *hw, unsigned long rate,
  133. unsigned long *parent_rate)
  134. {
  135. return calc_best_divided_rate(rate, *parent_rate,
  136. PB_DIV_MAX, PB_DIV_MIN);
  137. }
  138. static int pbclk_set_rate(struct clk_hw *hw, unsigned long rate,
  139. unsigned long parent_rate)
  140. {
  141. struct pic32_periph_clk *pb = clkhw_to_pbclk(hw);
  142. unsigned long flags;
  143. u32 v, div;
  144. int err;
  145. /* check & wait for DIV_READY */
  146. err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
  147. 1, LOCK_TIMEOUT_US);
  148. if (err)
  149. return err;
  150. /* calculate clkdiv and best rate */
  151. div = DIV_ROUND_CLOSEST(parent_rate, rate);
  152. spin_lock_irqsave(&pb->core->reg_lock, flags);
  153. /* apply new div */
  154. v = readl(pb->ctrl_reg);
  155. v &= ~PB_DIV_MASK;
  156. v |= (div - 1);
  157. pic32_syskey_unlock();
  158. writel(v, pb->ctrl_reg);
  159. spin_unlock_irqrestore(&pb->core->reg_lock, flags);
  160. /* wait again for DIV_READY */
  161. err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY,
  162. 1, LOCK_TIMEOUT_US);
  163. if (err)
  164. return err;
  165. /* confirm that new div is applied correctly */
  166. return (pbclk_read_pbdiv(pb) == div) ? 0 : -EBUSY;
  167. }
  168. const struct clk_ops pic32_pbclk_ops = {
  169. .enable = pbclk_enable,
  170. .disable = pbclk_disable,
  171. .is_enabled = pbclk_is_enabled,
  172. .recalc_rate = pbclk_recalc_rate,
  173. .round_rate = pbclk_round_rate,
  174. .set_rate = pbclk_set_rate,
  175. };
  176. struct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *desc,
  177. struct pic32_clk_common *core)
  178. {
  179. struct pic32_periph_clk *pbclk;
  180. struct clk *clk;
  181. pbclk = devm_kzalloc(core->dev, sizeof(*pbclk), GFP_KERNEL);
  182. if (!pbclk)
  183. return ERR_PTR(-ENOMEM);
  184. pbclk->hw.init = &desc->init_data;
  185. pbclk->core = core;
  186. pbclk->ctrl_reg = desc->ctrl_reg + core->iobase;
  187. clk = devm_clk_register(core->dev, &pbclk->hw);
  188. if (IS_ERR(clk)) {
  189. dev_err(core->dev, "%s: clk_register() failed\n", __func__);
  190. devm_kfree(core->dev, pbclk);
  191. }
  192. return clk;
  193. }
  194. /* Reference oscillator operations */
  195. struct pic32_ref_osc {
  196. struct clk_hw hw;
  197. void __iomem *ctrl_reg;
  198. const u32 *parent_map;
  199. struct pic32_clk_common *core;
  200. };
  201. #define clkhw_to_refosc(_hw) container_of(_hw, struct pic32_ref_osc, hw)
  202. static int roclk_is_enabled(struct clk_hw *hw)
  203. {
  204. struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
  205. return readl(refo->ctrl_reg) & REFO_ON;
  206. }
  207. static int roclk_enable(struct clk_hw *hw)
  208. {
  209. struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
  210. writel(REFO_ON | REFO_OE, PIC32_SET(refo->ctrl_reg));
  211. return 0;
  212. }
  213. static void roclk_disable(struct clk_hw *hw)
  214. {
  215. struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
  216. writel(REFO_ON | REFO_OE, PIC32_CLR(refo->ctrl_reg));
  217. }
  218. static int roclk_init(struct clk_hw *hw)
  219. {
  220. /* initialize clock in disabled state */
  221. roclk_disable(hw);
  222. return 0;
  223. }
  224. static u8 roclk_get_parent(struct clk_hw *hw)
  225. {
  226. struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
  227. u32 v, i;
  228. v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
  229. if (!refo->parent_map)
  230. return v;
  231. for (i = 0; i < clk_hw_get_num_parents(hw); i++)
  232. if (refo->parent_map[i] == v)
  233. return i;
  234. return -EINVAL;
  235. }
  236. static unsigned long roclk_calc_rate(unsigned long parent_rate,
  237. u32 rodiv, u32 rotrim)
  238. {
  239. u64 rate64;
  240. /* fout = fin / [2 * {div + (trim / 512)}]
  241. * = fin * 512 / [1024 * div + 2 * trim]
  242. * = fin * 256 / (512 * div + trim)
  243. * = (fin << 8) / ((div << 9) + trim)
  244. */
  245. if (rotrim) {
  246. rodiv = (rodiv << 9) + rotrim;
  247. rate64 = parent_rate;
  248. rate64 <<= 8;
  249. do_div(rate64, rodiv);
  250. } else if (rodiv) {
  251. rate64 = parent_rate / (rodiv << 1);
  252. } else {
  253. rate64 = parent_rate;
  254. }
  255. return rate64;
  256. }
  257. static void roclk_calc_div_trim(unsigned long rate,
  258. unsigned long parent_rate,
  259. u32 *rodiv_p, u32 *rotrim_p)
  260. {
  261. u32 div, rotrim, rodiv;
  262. u64 frac;
  263. /* Find integer approximation of floating-point arithmetic.
  264. * fout = fin / [2 * {rodiv + (rotrim / 512)}] ... (1)
  265. * i.e. fout = fin / 2 * DIV
  266. * whereas DIV = rodiv + (rotrim / 512)
  267. *
  268. * Since kernel does not perform floating-point arithmatic so
  269. * (rotrim/512) will be zero. And DIV & rodiv will result same.
  270. *
  271. * ie. fout = (fin * 256) / [(512 * rodiv) + rotrim] ... from (1)
  272. * ie. rotrim = ((fin * 256) / fout) - (512 * DIV)
  273. */
  274. if (parent_rate <= rate) {
  275. div = 0;
  276. frac = 0;
  277. rodiv = 0;
  278. rotrim = 0;
  279. } else {
  280. div = parent_rate / (rate << 1);
  281. frac = parent_rate;
  282. frac <<= 8;
  283. do_div(frac, rate);
  284. frac -= (u64)(div << 9);
  285. rodiv = (div > REFO_DIV_MASK) ? REFO_DIV_MASK : div;
  286. rotrim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : frac;
  287. }
  288. if (rodiv_p)
  289. *rodiv_p = rodiv;
  290. if (rotrim_p)
  291. *rotrim_p = rotrim;
  292. }
  293. static unsigned long roclk_recalc_rate(struct clk_hw *hw,
  294. unsigned long parent_rate)
  295. {
  296. struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
  297. u32 v, rodiv, rotrim;
  298. /* get rodiv */
  299. v = readl(refo->ctrl_reg);
  300. rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK;
  301. /* get trim */
  302. v = readl(refo->ctrl_reg + REFO_TRIM_REG);
  303. rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK;
  304. return roclk_calc_rate(parent_rate, rodiv, rotrim);
  305. }
  306. static long roclk_round_rate(struct clk_hw *hw, unsigned long rate,
  307. unsigned long *parent_rate)
  308. {
  309. u32 rotrim, rodiv;
  310. /* calculate dividers for new rate */
  311. roclk_calc_div_trim(rate, *parent_rate, &rodiv, &rotrim);
  312. /* caclulate new rate (rounding) based on new rodiv & rotrim */
  313. return roclk_calc_rate(*parent_rate, rodiv, rotrim);
  314. }
  315. static int roclk_determine_rate(struct clk_hw *hw,
  316. struct clk_rate_request *req)
  317. {
  318. struct clk_hw *parent_clk, *best_parent_clk = NULL;
  319. unsigned int i, delta, best_delta = -1;
  320. unsigned long parent_rate, best_parent_rate = 0;
  321. unsigned long best = 0, nearest_rate;
  322. /* find a parent which can generate nearest clkrate >= rate */
  323. for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
  324. /* get parent */
  325. parent_clk = clk_hw_get_parent_by_index(hw, i);
  326. if (!parent_clk)
  327. continue;
  328. /* skip if parent runs slower than target rate */
  329. parent_rate = clk_hw_get_rate(parent_clk);
  330. if (req->rate > parent_rate)
  331. continue;
  332. nearest_rate = roclk_round_rate(hw, req->rate, &parent_rate);
  333. delta = abs(nearest_rate - req->rate);
  334. if ((nearest_rate >= req->rate) && (delta < best_delta)) {
  335. best_parent_clk = parent_clk;
  336. best_parent_rate = parent_rate;
  337. best = nearest_rate;
  338. best_delta = delta;
  339. if (delta == 0)
  340. break;
  341. }
  342. }
  343. /* if no match found, retain old rate */
  344. if (!best_parent_clk) {
  345. pr_err("%s:%s, no parent found for rate %lu.\n",
  346. __func__, clk_hw_get_name(hw), req->rate);
  347. return clk_hw_get_rate(hw);
  348. }
  349. pr_debug("%s,rate %lu, best_parent(%s, %lu), best %lu, delta %d\n",
  350. clk_hw_get_name(hw), req->rate,
  351. clk_hw_get_name(best_parent_clk), best_parent_rate,
  352. best, best_delta);
  353. if (req->best_parent_rate)
  354. req->best_parent_rate = best_parent_rate;
  355. if (req->best_parent_hw)
  356. req->best_parent_hw = best_parent_clk;
  357. return best;
  358. }
  359. static int roclk_set_parent(struct clk_hw *hw, u8 index)
  360. {
  361. struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
  362. unsigned long flags;
  363. u32 v;
  364. int err;
  365. if (refo->parent_map)
  366. index = refo->parent_map[index];
  367. /* wait until ACTIVE bit is zero or timeout */
  368. err = readl_poll_timeout(refo->ctrl_reg, v, !(v & REFO_ACTIVE),
  369. 1, LOCK_TIMEOUT_US);
  370. if (err) {
  371. pr_err("%s: poll failed, clk active\n", clk_hw_get_name(hw));
  372. return err;
  373. }
  374. spin_lock_irqsave(&refo->core->reg_lock, flags);
  375. pic32_syskey_unlock();
  376. /* calculate & apply new */
  377. v = readl(refo->ctrl_reg);
  378. v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
  379. v |= index << REFO_SEL_SHIFT;
  380. writel(v, refo->ctrl_reg);
  381. spin_unlock_irqrestore(&refo->core->reg_lock, flags);
  382. return 0;
  383. }
  384. static int roclk_set_rate_and_parent(struct clk_hw *hw,
  385. unsigned long rate,
  386. unsigned long parent_rate,
  387. u8 index)
  388. {
  389. struct pic32_ref_osc *refo = clkhw_to_refosc(hw);
  390. unsigned long flags;
  391. u32 trim, rodiv, v;
  392. int err;
  393. /* calculate new rodiv & rotrim for new rate */
  394. roclk_calc_div_trim(rate, parent_rate, &rodiv, &trim);
  395. pr_debug("parent_rate = %lu, rate = %lu, div = %d, trim = %d\n",
  396. parent_rate, rate, rodiv, trim);
  397. /* wait till source change is active */
  398. err = readl_poll_timeout(refo->ctrl_reg, v,
  399. !(v & (REFO_ACTIVE | REFO_DIVSW_EN)),
  400. 1, LOCK_TIMEOUT_US);
  401. if (err) {
  402. pr_err("%s: poll timedout, clock is still active\n", __func__);
  403. return err;
  404. }
  405. spin_lock_irqsave(&refo->core->reg_lock, flags);
  406. v = readl(refo->ctrl_reg);
  407. pic32_syskey_unlock();
  408. /* apply parent, if required */
  409. if (refo->parent_map)
  410. index = refo->parent_map[index];
  411. v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
  412. v |= index << REFO_SEL_SHIFT;
  413. /* apply RODIV */
  414. v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT);
  415. v |= rodiv << REFO_DIV_SHIFT;
  416. writel(v, refo->ctrl_reg);
  417. /* apply ROTRIM */
  418. v = readl(refo->ctrl_reg + REFO_TRIM_REG);
  419. v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT);
  420. v |= trim << REFO_TRIM_SHIFT;
  421. writel(v, refo->ctrl_reg + REFO_TRIM_REG);
  422. /* enable & activate divider switching */
  423. writel(REFO_ON | REFO_DIVSW_EN, PIC32_SET(refo->ctrl_reg));
  424. /* wait till divswen is in-progress */
  425. err = readl_poll_timeout_atomic(refo->ctrl_reg, v, !(v & REFO_DIVSW_EN),
  426. 1, LOCK_TIMEOUT_US);
  427. /* leave the clk gated as it was */
  428. writel(REFO_ON, PIC32_CLR(refo->ctrl_reg));
  429. spin_unlock_irqrestore(&refo->core->reg_lock, flags);
  430. return err;
  431. }
  432. static int roclk_set_rate(struct clk_hw *hw, unsigned long rate,
  433. unsigned long parent_rate)
  434. {
  435. u8 index = roclk_get_parent(hw);
  436. return roclk_set_rate_and_parent(hw, rate, parent_rate, index);
  437. }
  438. const struct clk_ops pic32_roclk_ops = {
  439. .enable = roclk_enable,
  440. .disable = roclk_disable,
  441. .is_enabled = roclk_is_enabled,
  442. .get_parent = roclk_get_parent,
  443. .set_parent = roclk_set_parent,
  444. .determine_rate = roclk_determine_rate,
  445. .recalc_rate = roclk_recalc_rate,
  446. .set_rate_and_parent = roclk_set_rate_and_parent,
  447. .set_rate = roclk_set_rate,
  448. .init = roclk_init,
  449. };
  450. struct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data,
  451. struct pic32_clk_common *core)
  452. {
  453. struct pic32_ref_osc *refo;
  454. struct clk *clk;
  455. refo = devm_kzalloc(core->dev, sizeof(*refo), GFP_KERNEL);
  456. if (!refo)
  457. return ERR_PTR(-ENOMEM);
  458. refo->core = core;
  459. refo->hw.init = &data->init_data;
  460. refo->ctrl_reg = data->ctrl_reg + core->iobase;
  461. refo->parent_map = data->parent_map;
  462. clk = devm_clk_register(core->dev, &refo->hw);
  463. if (IS_ERR(clk))
  464. dev_err(core->dev, "%s: clk_register() failed\n", __func__);
  465. return clk;
  466. }
  467. struct pic32_sys_pll {
  468. struct clk_hw hw;
  469. void __iomem *ctrl_reg;
  470. void __iomem *status_reg;
  471. u32 lock_mask;
  472. u32 idiv; /* PLL iclk divider, treated fixed */
  473. struct pic32_clk_common *core;
  474. };
  475. #define clkhw_to_spll(_hw) container_of(_hw, struct pic32_sys_pll, hw)
  476. static inline u32 spll_odiv_to_divider(u32 odiv)
  477. {
  478. odiv = clamp_val(odiv, PLL_ODIV_MIN, PLL_ODIV_MAX);
  479. return 1 << odiv;
  480. }
  481. static unsigned long spll_calc_mult_div(struct pic32_sys_pll *pll,
  482. unsigned long rate,
  483. unsigned long parent_rate,
  484. u32 *mult_p, u32 *odiv_p)
  485. {
  486. u32 mul, div, best_mul = 1, best_div = 1;
  487. unsigned long new_rate, best_rate = rate;
  488. unsigned int best_delta = -1, delta, match_found = 0;
  489. u64 rate64;
  490. parent_rate /= pll->idiv;
  491. for (mul = 1; mul <= PLL_MULT_MAX; mul++) {
  492. for (div = PLL_ODIV_MIN; div <= PLL_ODIV_MAX; div++) {
  493. rate64 = parent_rate;
  494. rate64 *= mul;
  495. do_div(rate64, 1 << div);
  496. new_rate = rate64;
  497. delta = abs(rate - new_rate);
  498. if ((new_rate >= rate) && (delta < best_delta)) {
  499. best_delta = delta;
  500. best_rate = new_rate;
  501. best_mul = mul;
  502. best_div = div;
  503. match_found = 1;
  504. }
  505. }
  506. }
  507. if (!match_found) {
  508. pr_warn("spll: no match found\n");
  509. return 0;
  510. }
  511. pr_debug("rate %lu, par_rate %lu/mult %u, div %u, best_rate %lu\n",
  512. rate, parent_rate, best_mul, best_div, best_rate);
  513. if (mult_p)
  514. *mult_p = best_mul - 1;
  515. if (odiv_p)
  516. *odiv_p = best_div;
  517. return best_rate;
  518. }
  519. static unsigned long spll_clk_recalc_rate(struct clk_hw *hw,
  520. unsigned long parent_rate)
  521. {
  522. struct pic32_sys_pll *pll = clkhw_to_spll(hw);
  523. unsigned long pll_in_rate;
  524. u32 mult, odiv, div, v;
  525. u64 rate64;
  526. v = readl(pll->ctrl_reg);
  527. odiv = ((v >> PLL_ODIV_SHIFT) & PLL_ODIV_MASK);
  528. mult = ((v >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
  529. div = spll_odiv_to_divider(odiv);
  530. /* pll_in_rate = parent_rate / idiv
  531. * pll_out_rate = pll_in_rate * mult / div;
  532. */
  533. pll_in_rate = parent_rate / pll->idiv;
  534. rate64 = pll_in_rate;
  535. rate64 *= mult;
  536. do_div(rate64, div);
  537. return rate64;
  538. }
  539. static long spll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  540. unsigned long *parent_rate)
  541. {
  542. struct pic32_sys_pll *pll = clkhw_to_spll(hw);
  543. return spll_calc_mult_div(pll, rate, *parent_rate, NULL, NULL);
  544. }
  545. static int spll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  546. unsigned long parent_rate)
  547. {
  548. struct pic32_sys_pll *pll = clkhw_to_spll(hw);
  549. unsigned long ret, flags;
  550. u32 mult, odiv, v;
  551. int err;
  552. ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv);
  553. if (!ret)
  554. return -EINVAL;
  555. /*
  556. * We can't change SPLL counters when it is in-active use
  557. * by SYSCLK. So check before applying new counters/rate.
  558. */
  559. /* Is spll_clk active parent of sys_clk ? */
  560. if (unlikely(clk_hw_get_parent(pic32_sclk_hw) == hw)) {
  561. pr_err("%s: failed, clk in-use\n", __func__);
  562. return -EBUSY;
  563. }
  564. spin_lock_irqsave(&pll->core->reg_lock, flags);
  565. /* apply new multiplier & divisor */
  566. v = readl(pll->ctrl_reg);
  567. v &= ~(PLL_MULT_MASK << PLL_MULT_SHIFT);
  568. v &= ~(PLL_ODIV_MASK << PLL_ODIV_SHIFT);
  569. v |= (mult << PLL_MULT_SHIFT) | (odiv << PLL_ODIV_SHIFT);
  570. /* sys unlock before write */
  571. pic32_syskey_unlock();
  572. writel(v, pll->ctrl_reg);
  573. cpu_relax();
  574. /* insert few nops (5-stage) to ensure CPU does not hang */
  575. cpu_nop5();
  576. cpu_nop5();
  577. /* Wait until PLL is locked (maximum 100 usecs). */
  578. err = readl_poll_timeout_atomic(pll->status_reg, v,
  579. v & pll->lock_mask, 1, 100);
  580. spin_unlock_irqrestore(&pll->core->reg_lock, flags);
  581. return err;
  582. }
  583. /* SPLL clock operation */
  584. const struct clk_ops pic32_spll_ops = {
  585. .recalc_rate = spll_clk_recalc_rate,
  586. .round_rate = spll_clk_round_rate,
  587. .set_rate = spll_clk_set_rate,
  588. };
  589. struct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data,
  590. struct pic32_clk_common *core)
  591. {
  592. struct pic32_sys_pll *spll;
  593. struct clk *clk;
  594. spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL);
  595. if (!spll)
  596. return ERR_PTR(-ENOMEM);
  597. spll->core = core;
  598. spll->hw.init = &data->init_data;
  599. spll->ctrl_reg = data->ctrl_reg + core->iobase;
  600. spll->status_reg = data->status_reg + core->iobase;
  601. spll->lock_mask = data->lock_mask;
  602. /* cache PLL idiv; PLL driver uses it as constant.*/
  603. spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK;
  604. spll->idiv += 1;
  605. clk = devm_clk_register(core->dev, &spll->hw);
  606. if (IS_ERR(clk))
  607. dev_err(core->dev, "sys_pll: clk_register() failed\n");
  608. return clk;
  609. }
  610. /* System mux clock(aka SCLK) */
  611. struct pic32_sys_clk {
  612. struct clk_hw hw;
  613. void __iomem *mux_reg;
  614. void __iomem *slew_reg;
  615. u32 slew_div;
  616. const u32 *parent_map;
  617. struct pic32_clk_common *core;
  618. };
  619. #define clkhw_to_sys_clk(_hw) container_of(_hw, struct pic32_sys_clk, hw)
  620. static unsigned long sclk_get_rate(struct clk_hw *hw, unsigned long parent_rate)
  621. {
  622. struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
  623. u32 div;
  624. div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV;
  625. div += 1; /* sys-div to divider */
  626. return parent_rate / div;
  627. }
  628. static long sclk_round_rate(struct clk_hw *hw, unsigned long rate,
  629. unsigned long *parent_rate)
  630. {
  631. return calc_best_divided_rate(rate, *parent_rate, SLEW_SYSDIV, 1);
  632. }
  633. static int sclk_set_rate(struct clk_hw *hw,
  634. unsigned long rate, unsigned long parent_rate)
  635. {
  636. struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
  637. unsigned long flags;
  638. u32 v, div;
  639. int err;
  640. div = parent_rate / rate;
  641. spin_lock_irqsave(&sclk->core->reg_lock, flags);
  642. /* apply new div */
  643. v = readl(sclk->slew_reg);
  644. v &= ~(SLEW_SYSDIV << SLEW_SYSDIV_SHIFT);
  645. v |= (div - 1) << SLEW_SYSDIV_SHIFT;
  646. pic32_syskey_unlock();
  647. writel(v, sclk->slew_reg);
  648. /* wait until BUSY is cleared */
  649. err = readl_poll_timeout_atomic(sclk->slew_reg, v,
  650. !(v & SLEW_BUSY), 1, LOCK_TIMEOUT_US);
  651. spin_unlock_irqrestore(&sclk->core->reg_lock, flags);
  652. return err;
  653. }
  654. static u8 sclk_get_parent(struct clk_hw *hw)
  655. {
  656. struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
  657. u32 i, v;
  658. v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK;
  659. if (!sclk->parent_map)
  660. return v;
  661. for (i = 0; i < clk_hw_get_num_parents(hw); i++)
  662. if (sclk->parent_map[i] == v)
  663. return i;
  664. return -EINVAL;
  665. }
  666. static int sclk_set_parent(struct clk_hw *hw, u8 index)
  667. {
  668. struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
  669. unsigned long flags;
  670. u32 nosc, cosc, v;
  671. int err;
  672. spin_lock_irqsave(&sclk->core->reg_lock, flags);
  673. /* find new_osc */
  674. nosc = sclk->parent_map ? sclk->parent_map[index] : index;
  675. /* set new parent */
  676. v = readl(sclk->mux_reg);
  677. v &= ~(OSC_NEW_MASK << OSC_NEW_SHIFT);
  678. v |= nosc << OSC_NEW_SHIFT;
  679. pic32_syskey_unlock();
  680. writel(v, sclk->mux_reg);
  681. /* initate switch */
  682. writel(OSC_SWEN, PIC32_SET(sclk->mux_reg));
  683. cpu_relax();
  684. /* add nop to flush pipeline (as cpu_clk is in-flux) */
  685. cpu_nop5();
  686. /* wait for SWEN bit to clear */
  687. err = readl_poll_timeout_atomic(sclk->slew_reg, v,
  688. !(v & OSC_SWEN), 1, LOCK_TIMEOUT_US);
  689. spin_unlock_irqrestore(&sclk->core->reg_lock, flags);
  690. /*
  691. * SCLK clock-switching logic might reject a clock switching request
  692. * if pre-requisites (like new clk_src not present or unstable) are
  693. * not met.
  694. * So confirm before claiming success.
  695. */
  696. cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK;
  697. if (cosc != nosc) {
  698. pr_err("%s: err, failed to set_parent() to %d, current %d\n",
  699. clk_hw_get_name(hw), nosc, cosc);
  700. err = -EBUSY;
  701. }
  702. return err;
  703. }
  704. static int sclk_init(struct clk_hw *hw)
  705. {
  706. struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw);
  707. unsigned long flags;
  708. u32 v;
  709. /* Maintain reference to this clk, required in spll_clk_set_rate() */
  710. pic32_sclk_hw = hw;
  711. /* apply slew divider on both up and down scaling */
  712. if (sclk->slew_div) {
  713. spin_lock_irqsave(&sclk->core->reg_lock, flags);
  714. v = readl(sclk->slew_reg);
  715. v &= ~(SLEW_DIV << SLEW_DIV_SHIFT);
  716. v |= sclk->slew_div << SLEW_DIV_SHIFT;
  717. v |= SLEW_DOWNEN | SLEW_UPEN;
  718. writel(v, sclk->slew_reg);
  719. spin_unlock_irqrestore(&sclk->core->reg_lock, flags);
  720. }
  721. return 0;
  722. }
  723. /* sclk with post-divider */
  724. const struct clk_ops pic32_sclk_ops = {
  725. .get_parent = sclk_get_parent,
  726. .set_parent = sclk_set_parent,
  727. .round_rate = sclk_round_rate,
  728. .set_rate = sclk_set_rate,
  729. .recalc_rate = sclk_get_rate,
  730. .init = sclk_init,
  731. .determine_rate = __clk_mux_determine_rate,
  732. };
  733. /* sclk with no slew and no post-divider */
  734. const struct clk_ops pic32_sclk_no_div_ops = {
  735. .get_parent = sclk_get_parent,
  736. .set_parent = sclk_set_parent,
  737. .init = sclk_init,
  738. .determine_rate = __clk_mux_determine_rate,
  739. };
  740. struct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data,
  741. struct pic32_clk_common *core)
  742. {
  743. struct pic32_sys_clk *sclk;
  744. struct clk *clk;
  745. sclk = devm_kzalloc(core->dev, sizeof(*sclk), GFP_KERNEL);
  746. if (!sclk)
  747. return ERR_PTR(-ENOMEM);
  748. sclk->core = core;
  749. sclk->hw.init = &data->init_data;
  750. sclk->mux_reg = data->mux_reg + core->iobase;
  751. sclk->slew_reg = data->slew_reg + core->iobase;
  752. sclk->slew_div = data->slew_div;
  753. sclk->parent_map = data->parent_map;
  754. clk = devm_clk_register(core->dev, &sclk->hw);
  755. if (IS_ERR(clk))
  756. dev_err(core->dev, "%s: clk register failed\n", __func__);
  757. return clk;
  758. }
  759. /* secondary oscillator */
  760. struct pic32_sec_osc {
  761. struct clk_hw hw;
  762. void __iomem *enable_reg;
  763. void __iomem *status_reg;
  764. u32 enable_mask;
  765. u32 status_mask;
  766. unsigned long fixed_rate;
  767. struct pic32_clk_common *core;
  768. };
  769. #define clkhw_to_sosc(_hw) container_of(_hw, struct pic32_sec_osc, hw)
  770. static int sosc_clk_enable(struct clk_hw *hw)
  771. {
  772. struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);
  773. u32 v;
  774. /* enable SOSC */
  775. pic32_syskey_unlock();
  776. writel(sosc->enable_mask, PIC32_SET(sosc->enable_reg));
  777. /* wait till warm-up period expires or ready-status is updated */
  778. return readl_poll_timeout_atomic(sosc->status_reg, v,
  779. v & sosc->status_mask, 1, 100);
  780. }
  781. static void sosc_clk_disable(struct clk_hw *hw)
  782. {
  783. struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);
  784. pic32_syskey_unlock();
  785. writel(sosc->enable_mask, PIC32_CLR(sosc->enable_reg));
  786. }
  787. static int sosc_clk_is_enabled(struct clk_hw *hw)
  788. {
  789. struct pic32_sec_osc *sosc = clkhw_to_sosc(hw);
  790. u32 enabled, ready;
  791. /* check enabled and ready status */
  792. enabled = readl(sosc->enable_reg) & sosc->enable_mask;
  793. ready = readl(sosc->status_reg) & sosc->status_mask;
  794. return enabled && ready;
  795. }
  796. static unsigned long sosc_clk_calc_rate(struct clk_hw *hw,
  797. unsigned long parent_rate)
  798. {
  799. return clkhw_to_sosc(hw)->fixed_rate;
  800. }
  801. const struct clk_ops pic32_sosc_ops = {
  802. .enable = sosc_clk_enable,
  803. .disable = sosc_clk_disable,
  804. .is_enabled = sosc_clk_is_enabled,
  805. .recalc_rate = sosc_clk_calc_rate,
  806. };
  807. struct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data,
  808. struct pic32_clk_common *core)
  809. {
  810. struct pic32_sec_osc *sosc;
  811. sosc = devm_kzalloc(core->dev, sizeof(*sosc), GFP_KERNEL);
  812. if (!sosc)
  813. return ERR_PTR(-ENOMEM);
  814. sosc->core = core;
  815. sosc->hw.init = &data->init_data;
  816. sosc->fixed_rate = data->fixed_rate;
  817. sosc->enable_mask = data->enable_mask;
  818. sosc->status_mask = data->status_mask;
  819. sosc->enable_reg = data->enable_reg + core->iobase;
  820. sosc->status_reg = data->status_reg + core->iobase;
  821. return devm_clk_register(core->dev, &sosc->hw);
  822. }