clk-pll.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: James Liao <jamesjj.liao@mediatek.com>
  5. */
  6. #include <linux/of.h>
  7. #include <linux/of_address.h>
  8. #include <linux/io.h>
  9. #include <linux/slab.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/delay.h>
  12. #include "clk-mtk.h"
  13. #define REG_CON0 0
  14. #define REG_CON1 4
  15. #define CON0_BASE_EN BIT(0)
  16. #define CON0_PWR_ON BIT(0)
  17. #define CON0_ISO_EN BIT(1)
  18. #define PCW_CHG_MASK BIT(31)
  19. #define AUDPLL_TUNER_EN BIT(31)
  20. #define POSTDIV_MASK 0x7
  21. /* default 7 bits integer, can be overridden with pcwibits. */
  22. #define INTEGER_BITS 7
  23. /*
  24. * MediaTek PLLs are configured through their pcw value. The pcw value describes
  25. * a divider in the PLL feedback loop which consists of 7 bits for the integer
  26. * part and the remaining bits (if present) for the fractional part. Also they
  27. * have a 3 bit power-of-two post divider.
  28. */
  29. struct mtk_clk_pll {
  30. struct clk_hw hw;
  31. void __iomem *base_addr;
  32. void __iomem *pd_addr;
  33. void __iomem *pwr_addr;
  34. void __iomem *tuner_addr;
  35. void __iomem *tuner_en_addr;
  36. void __iomem *pcw_addr;
  37. void __iomem *pcw_chg_addr;
  38. const struct mtk_pll_data *data;
  39. };
  40. static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
  41. {
  42. return container_of(hw, struct mtk_clk_pll, hw);
  43. }
  44. static int mtk_pll_is_prepared(struct clk_hw *hw)
  45. {
  46. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  47. return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
  48. }
  49. static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
  50. u32 pcw, int postdiv)
  51. {
  52. int pcwbits = pll->data->pcwbits;
  53. int pcwfbits = 0;
  54. int ibits;
  55. u64 vco;
  56. u8 c = 0;
  57. /* The fractional part of the PLL divider. */
  58. ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
  59. if (pcwbits > ibits)
  60. pcwfbits = pcwbits - ibits;
  61. vco = (u64)fin * pcw;
  62. if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
  63. c = 1;
  64. vco >>= pcwfbits;
  65. if (c)
  66. vco++;
  67. return ((unsigned long)vco + postdiv - 1) / postdiv;
  68. }
  69. static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
  70. {
  71. u32 r;
  72. if (pll->tuner_en_addr) {
  73. r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
  74. writel(r, pll->tuner_en_addr);
  75. } else if (pll->tuner_addr) {
  76. r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
  77. writel(r, pll->tuner_addr);
  78. }
  79. }
  80. static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
  81. {
  82. u32 r;
  83. if (pll->tuner_en_addr) {
  84. r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
  85. writel(r, pll->tuner_en_addr);
  86. } else if (pll->tuner_addr) {
  87. r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
  88. writel(r, pll->tuner_addr);
  89. }
  90. }
  91. static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
  92. int postdiv)
  93. {
  94. u32 chg, val;
  95. /* disable tuner */
  96. __mtk_pll_tuner_disable(pll);
  97. /* set postdiv */
  98. val = readl(pll->pd_addr);
  99. val &= ~(POSTDIV_MASK << pll->data->pd_shift);
  100. val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
  101. /* postdiv and pcw need to set at the same time if on same register */
  102. if (pll->pd_addr != pll->pcw_addr) {
  103. writel(val, pll->pd_addr);
  104. val = readl(pll->pcw_addr);
  105. }
  106. /* set pcw */
  107. val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
  108. pll->data->pcw_shift);
  109. val |= pcw << pll->data->pcw_shift;
  110. writel(val, pll->pcw_addr);
  111. chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
  112. writel(chg, pll->pcw_chg_addr);
  113. if (pll->tuner_addr)
  114. writel(val + 1, pll->tuner_addr);
  115. /* restore tuner_en */
  116. __mtk_pll_tuner_enable(pll);
  117. udelay(20);
  118. }
  119. /*
  120. * mtk_pll_calc_values - calculate good values for a given input frequency.
  121. * @pll: The pll
  122. * @pcw: The pcw value (output)
  123. * @postdiv: The post divider (output)
  124. * @freq: The desired target frequency
  125. * @fin: The input frequency
  126. *
  127. */
  128. static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
  129. u32 freq, u32 fin)
  130. {
  131. unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
  132. const struct mtk_pll_div_table *div_table = pll->data->div_table;
  133. u64 _pcw;
  134. int ibits;
  135. u32 val;
  136. if (freq > pll->data->fmax)
  137. freq = pll->data->fmax;
  138. if (div_table) {
  139. if (freq > div_table[0].freq)
  140. freq = div_table[0].freq;
  141. for (val = 0; div_table[val + 1].freq != 0; val++) {
  142. if (freq > div_table[val + 1].freq)
  143. break;
  144. }
  145. *postdiv = 1 << val;
  146. } else {
  147. for (val = 0; val < 5; val++) {
  148. *postdiv = 1 << val;
  149. if ((u64)freq * *postdiv >= fmin)
  150. break;
  151. }
  152. }
  153. /* _pcw = freq * postdiv / fin * 2^pcwfbits */
  154. ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
  155. _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
  156. do_div(_pcw, fin);
  157. *pcw = (u32)_pcw;
  158. }
  159. static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
  160. unsigned long parent_rate)
  161. {
  162. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  163. u32 pcw = 0;
  164. u32 postdiv;
  165. mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
  166. mtk_pll_set_rate_regs(pll, pcw, postdiv);
  167. return 0;
  168. }
  169. static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
  170. unsigned long parent_rate)
  171. {
  172. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  173. u32 postdiv;
  174. u32 pcw;
  175. postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
  176. postdiv = 1 << postdiv;
  177. pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
  178. pcw &= GENMASK(pll->data->pcwbits - 1, 0);
  179. return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
  180. }
  181. static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
  182. unsigned long *prate)
  183. {
  184. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  185. u32 pcw = 0;
  186. int postdiv;
  187. mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
  188. return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
  189. }
  190. static int mtk_pll_prepare(struct clk_hw *hw)
  191. {
  192. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  193. u32 r;
  194. r = readl(pll->pwr_addr) | CON0_PWR_ON;
  195. writel(r, pll->pwr_addr);
  196. udelay(1);
  197. r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
  198. writel(r, pll->pwr_addr);
  199. udelay(1);
  200. r = readl(pll->base_addr + REG_CON0);
  201. r |= pll->data->en_mask;
  202. writel(r, pll->base_addr + REG_CON0);
  203. __mtk_pll_tuner_enable(pll);
  204. udelay(20);
  205. if (pll->data->flags & HAVE_RST_BAR) {
  206. r = readl(pll->base_addr + REG_CON0);
  207. r |= pll->data->rst_bar_mask;
  208. writel(r, pll->base_addr + REG_CON0);
  209. }
  210. return 0;
  211. }
  212. static void mtk_pll_unprepare(struct clk_hw *hw)
  213. {
  214. struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
  215. u32 r;
  216. if (pll->data->flags & HAVE_RST_BAR) {
  217. r = readl(pll->base_addr + REG_CON0);
  218. r &= ~pll->data->rst_bar_mask;
  219. writel(r, pll->base_addr + REG_CON0);
  220. }
  221. __mtk_pll_tuner_disable(pll);
  222. r = readl(pll->base_addr + REG_CON0);
  223. r &= ~CON0_BASE_EN;
  224. writel(r, pll->base_addr + REG_CON0);
  225. r = readl(pll->pwr_addr) | CON0_ISO_EN;
  226. writel(r, pll->pwr_addr);
  227. r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
  228. writel(r, pll->pwr_addr);
  229. }
  230. static const struct clk_ops mtk_pll_ops = {
  231. .is_prepared = mtk_pll_is_prepared,
  232. .prepare = mtk_pll_prepare,
  233. .unprepare = mtk_pll_unprepare,
  234. .recalc_rate = mtk_pll_recalc_rate,
  235. .round_rate = mtk_pll_round_rate,
  236. .set_rate = mtk_pll_set_rate,
  237. };
  238. static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
  239. void __iomem *base)
  240. {
  241. struct mtk_clk_pll *pll;
  242. struct clk_init_data init = {};
  243. struct clk *clk;
  244. const char *parent_name = "clk26m";
  245. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  246. if (!pll)
  247. return ERR_PTR(-ENOMEM);
  248. pll->base_addr = base + data->reg;
  249. pll->pwr_addr = base + data->pwr_reg;
  250. pll->pd_addr = base + data->pd_reg;
  251. pll->pcw_addr = base + data->pcw_reg;
  252. if (data->pcw_chg_reg)
  253. pll->pcw_chg_addr = base + data->pcw_chg_reg;
  254. else
  255. pll->pcw_chg_addr = pll->base_addr + REG_CON1;
  256. if (data->tuner_reg)
  257. pll->tuner_addr = base + data->tuner_reg;
  258. if (data->tuner_en_reg)
  259. pll->tuner_en_addr = base + data->tuner_en_reg;
  260. pll->hw.init = &init;
  261. pll->data = data;
  262. init.name = data->name;
  263. init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
  264. init.ops = &mtk_pll_ops;
  265. if (data->parent_name)
  266. init.parent_names = &data->parent_name;
  267. else
  268. init.parent_names = &parent_name;
  269. init.num_parents = 1;
  270. clk = clk_register(NULL, &pll->hw);
  271. if (IS_ERR(clk))
  272. kfree(pll);
  273. return clk;
  274. }
  275. void mtk_clk_register_plls(struct device_node *node,
  276. const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
  277. {
  278. void __iomem *base;
  279. int i;
  280. struct clk *clk;
  281. base = of_iomap(node, 0);
  282. if (!base) {
  283. pr_err("%s(): ioremap failed\n", __func__);
  284. return;
  285. }
  286. for (i = 0; i < num_plls; i++) {
  287. const struct mtk_pll_data *pll = &plls[i];
  288. clk = mtk_clk_register_pll(pll, base);
  289. if (IS_ERR(clk)) {
  290. pr_err("Failed to register clk %s: %ld\n",
  291. pll->name, PTR_ERR(clk));
  292. continue;
  293. }
  294. clk_data->clks[pll->id] = clk;
  295. }
  296. }