clk-mtk.h 5.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: James Liao <jamesjj.liao@mediatek.com>
  5. */
  6. #ifndef __DRV_CLK_MTK_H
  7. #define __DRV_CLK_MTK_H
  8. #include <linux/regmap.h>
  9. #include <linux/bitops.h>
  10. #include <linux/clk-provider.h>
  11. struct clk;
  12. struct clk_onecell_data;
  13. #define MAX_MUX_GATE_BIT 31
  14. #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
  15. #define MHZ (1000 * 1000)
  16. struct mtk_fixed_clk {
  17. int id;
  18. const char *name;
  19. const char *parent;
  20. unsigned long rate;
  21. };
  22. #define FIXED_CLK(_id, _name, _parent, _rate) { \
  23. .id = _id, \
  24. .name = _name, \
  25. .parent = _parent, \
  26. .rate = _rate, \
  27. }
  28. void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
  29. int num, struct clk_onecell_data *clk_data);
  30. struct mtk_fixed_factor {
  31. int id;
  32. const char *name;
  33. const char *parent_name;
  34. int mult;
  35. int div;
  36. };
  37. #define FACTOR(_id, _name, _parent, _mult, _div) { \
  38. .id = _id, \
  39. .name = _name, \
  40. .parent_name = _parent, \
  41. .mult = _mult, \
  42. .div = _div, \
  43. }
  44. void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
  45. int num, struct clk_onecell_data *clk_data);
  46. struct mtk_composite {
  47. int id;
  48. const char *name;
  49. const char * const *parent_names;
  50. const char *parent;
  51. unsigned flags;
  52. uint32_t mux_reg;
  53. uint32_t divider_reg;
  54. uint32_t gate_reg;
  55. signed char mux_shift;
  56. signed char mux_width;
  57. signed char gate_shift;
  58. signed char divider_shift;
  59. signed char divider_width;
  60. u8 mux_flags;
  61. signed char num_parents;
  62. };
  63. #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
  64. _width, _gate, _flags, _muxflags) { \
  65. .id = _id, \
  66. .name = _name, \
  67. .mux_reg = _reg, \
  68. .mux_shift = _shift, \
  69. .mux_width = _width, \
  70. .gate_reg = _reg, \
  71. .gate_shift = _gate, \
  72. .divider_shift = -1, \
  73. .parent_names = _parents, \
  74. .num_parents = ARRAY_SIZE(_parents), \
  75. .flags = _flags, \
  76. .mux_flags = _muxflags, \
  77. }
  78. /*
  79. * In case the rate change propagation to parent clocks is undesirable,
  80. * this macro allows to specify the clock flags manually.
  81. */
  82. #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
  83. _gate, _flags) \
  84. MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
  85. _shift, _width, _gate, _flags, 0)
  86. /*
  87. * Unless necessary, all MUX_GATE clocks propagate rate changes to their
  88. * parent clock by default.
  89. */
  90. #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
  91. MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
  92. _gate, CLK_SET_RATE_PARENT)
  93. #define MUX(_id, _name, _parents, _reg, _shift, _width) \
  94. MUX_FLAGS(_id, _name, _parents, _reg, \
  95. _shift, _width, CLK_SET_RATE_PARENT)
  96. #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
  97. .id = _id, \
  98. .name = _name, \
  99. .mux_reg = _reg, \
  100. .mux_shift = _shift, \
  101. .mux_width = _width, \
  102. .gate_shift = -1, \
  103. .divider_shift = -1, \
  104. .parent_names = _parents, \
  105. .num_parents = ARRAY_SIZE(_parents), \
  106. .flags = _flags, \
  107. }
  108. #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
  109. _div_width, _div_shift) { \
  110. .id = _id, \
  111. .parent = _parent, \
  112. .name = _name, \
  113. .divider_reg = _div_reg, \
  114. .divider_shift = _div_shift, \
  115. .divider_width = _div_width, \
  116. .gate_reg = _gate_reg, \
  117. .gate_shift = _gate_shift, \
  118. .mux_shift = -1, \
  119. .flags = 0, \
  120. }
  121. struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
  122. void __iomem *base, spinlock_t *lock);
  123. void mtk_clk_register_composites(const struct mtk_composite *mcs,
  124. int num, void __iomem *base, spinlock_t *lock,
  125. struct clk_onecell_data *clk_data);
  126. struct mtk_gate_regs {
  127. u32 sta_ofs;
  128. u32 clr_ofs;
  129. u32 set_ofs;
  130. };
  131. struct mtk_gate {
  132. int id;
  133. const char *name;
  134. const char *parent_name;
  135. const struct mtk_gate_regs *regs;
  136. int shift;
  137. const struct clk_ops *ops;
  138. unsigned long flags;
  139. };
  140. int mtk_clk_register_gates(struct device_node *node,
  141. const struct mtk_gate *clks, int num,
  142. struct clk_onecell_data *clk_data);
  143. int mtk_clk_register_gates_with_dev(struct device_node *node,
  144. const struct mtk_gate *clks,
  145. int num, struct clk_onecell_data *clk_data,
  146. struct device *dev);
  147. struct mtk_clk_divider {
  148. int id;
  149. const char *name;
  150. const char *parent_name;
  151. unsigned long flags;
  152. u32 div_reg;
  153. unsigned char div_shift;
  154. unsigned char div_width;
  155. unsigned char clk_divider_flags;
  156. const struct clk_div_table *clk_div_table;
  157. };
  158. #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
  159. .id = _id, \
  160. .name = _name, \
  161. .parent_name = _parent, \
  162. .div_reg = _reg, \
  163. .div_shift = _shift, \
  164. .div_width = _width, \
  165. }
  166. void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
  167. int num, void __iomem *base, spinlock_t *lock,
  168. struct clk_onecell_data *clk_data);
  169. struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
  170. #define HAVE_RST_BAR BIT(0)
  171. #define PLL_AO BIT(1)
  172. struct mtk_pll_div_table {
  173. u32 div;
  174. unsigned long freq;
  175. };
  176. struct mtk_pll_data {
  177. int id;
  178. const char *name;
  179. uint32_t reg;
  180. uint32_t pwr_reg;
  181. uint32_t en_mask;
  182. uint32_t pd_reg;
  183. uint32_t tuner_reg;
  184. uint32_t tuner_en_reg;
  185. uint8_t tuner_en_bit;
  186. int pd_shift;
  187. unsigned int flags;
  188. const struct clk_ops *ops;
  189. u32 rst_bar_mask;
  190. unsigned long fmin;
  191. unsigned long fmax;
  192. int pcwbits;
  193. int pcwibits;
  194. uint32_t pcw_reg;
  195. int pcw_shift;
  196. uint32_t pcw_chg_reg;
  197. const struct mtk_pll_div_table *div_table;
  198. const char *parent_name;
  199. };
  200. void mtk_clk_register_plls(struct device_node *node,
  201. const struct mtk_pll_data *plls, int num_plls,
  202. struct clk_onecell_data *clk_data);
  203. struct clk *mtk_clk_register_ref2usb_tx(const char *name,
  204. const char *parent_name, void __iomem *reg);
  205. void mtk_register_reset_controller(struct device_node *np,
  206. unsigned int num_regs, int regofs);
  207. void mtk_register_reset_controller_set_clr(struct device_node *np,
  208. unsigned int num_regs, int regofs);
  209. #endif /* __DRV_CLK_MTK_H */