clk-mt8516-aud.c 1.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. * Author: James Liao <jamesjj.liao@mediatek.com>
  5. * Fabien Parent <fparent@baylibre.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include "clk-mtk.h"
  13. #include "clk-gate.h"
  14. #include <dt-bindings/clock/mt8516-clk.h>
  15. static const struct mtk_gate_regs aud_cg_regs = {
  16. .set_ofs = 0x0,
  17. .clr_ofs = 0x0,
  18. .sta_ofs = 0x0,
  19. };
  20. #define GATE_AUD(_id, _name, _parent, _shift) { \
  21. .id = _id, \
  22. .name = _name, \
  23. .parent_name = _parent, \
  24. .regs = &aud_cg_regs, \
  25. .shift = _shift, \
  26. .ops = &mtk_clk_gate_ops_no_setclr, \
  27. }
  28. static const struct mtk_gate aud_clks[] __initconst = {
  29. GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
  30. GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
  31. GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
  32. GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
  33. GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
  34. GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
  35. GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
  36. GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
  37. GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
  38. GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
  39. GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
  40. GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
  41. GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
  42. };
  43. static void __init mtk_audsys_init(struct device_node *node)
  44. {
  45. struct clk_onecell_data *clk_data;
  46. int r;
  47. clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
  48. mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
  49. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  50. if (r)
  51. pr_err("%s(): could not register clock provider: %d\n",
  52. __func__, r);
  53. }
  54. CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init);