clk-mt8183.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. #include <linux/delay.h>
  6. #include <linux/mfd/syscon.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_device.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #include "clk-mtk.h"
  13. #include "clk-mux.h"
  14. #include "clk-gate.h"
  15. #include <dt-bindings/clock/mt8183-clk.h>
  16. /* Infra global controller reset set register */
  17. #define INFRA_RST0_SET_OFFSET 0x120
  18. static DEFINE_SPINLOCK(mt8183_clk_lock);
  19. static const struct mtk_fixed_clk top_fixed_clks[] = {
  20. FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
  21. FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
  22. FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
  23. };
  24. static const struct mtk_fixed_factor top_early_divs[] = {
  25. FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
  26. };
  27. static const struct mtk_fixed_factor top_divs[] = {
  28. FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
  29. 2),
  30. FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
  31. 1),
  32. FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
  33. 2),
  34. FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
  35. 2),
  36. FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
  37. 4),
  38. FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
  39. 8),
  40. FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
  41. 16),
  42. FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
  43. 3),
  44. FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
  45. 2),
  46. FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
  47. 4),
  48. FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
  49. 8),
  50. FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
  51. 5),
  52. FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
  53. 2),
  54. FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
  55. 4),
  56. FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
  57. 7),
  58. FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
  59. 2),
  60. FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
  61. 4),
  62. FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
  63. 1),
  64. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
  65. 2),
  66. FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
  67. 2),
  68. FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
  69. 4),
  70. FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
  71. 8),
  72. FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
  73. 3),
  74. FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
  75. 2),
  76. FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
  77. 4),
  78. FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
  79. 8),
  80. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
  81. 5),
  82. FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
  83. 2),
  84. FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
  85. 4),
  86. FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
  87. 8),
  88. FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
  89. 7),
  90. FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
  91. 1),
  92. FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
  93. 2),
  94. FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
  95. 4),
  96. FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
  97. 8),
  98. FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
  99. 16),
  100. FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
  101. 32),
  102. FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
  103. 1),
  104. FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
  105. 2),
  106. FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
  107. 4),
  108. FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
  109. 8),
  110. FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
  111. 1),
  112. FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
  113. 2),
  114. FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
  115. 4),
  116. FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
  117. 8),
  118. FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
  119. 1),
  120. FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
  121. 2),
  122. FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
  123. 4),
  124. FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
  125. 8),
  126. FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
  127. 16),
  128. FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
  129. 1),
  130. FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
  131. 4),
  132. FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
  133. 2),
  134. FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
  135. 4),
  136. FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
  137. 5),
  138. FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
  139. 2),
  140. FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
  141. 4),
  142. FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
  143. 6),
  144. FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
  145. 7),
  146. FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
  147. 1),
  148. FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
  149. 1),
  150. FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
  151. 2),
  152. FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
  153. 4),
  154. FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
  155. 8),
  156. FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
  157. 16),
  158. FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
  159. 1),
  160. FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
  161. 2),
  162. FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
  163. 4),
  164. FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
  165. 8),
  166. FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
  167. 16),
  168. FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
  169. 2),
  170. FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
  171. 16),
  172. };
  173. static const char * const axi_parents[] = {
  174. "clk26m",
  175. "syspll_d2_d4",
  176. "syspll_d7",
  177. "osc_d4"
  178. };
  179. static const char * const mm_parents[] = {
  180. "clk26m",
  181. "mmpll_d7",
  182. "syspll_d3",
  183. "univpll_d2_d2",
  184. "syspll_d2_d2",
  185. "syspll_d3_d2"
  186. };
  187. static const char * const img_parents[] = {
  188. "clk26m",
  189. "mmpll_d6",
  190. "univpll_d3",
  191. "syspll_d3",
  192. "univpll_d2_d2",
  193. "syspll_d2_d2",
  194. "univpll_d3_d2",
  195. "syspll_d3_d2"
  196. };
  197. static const char * const cam_parents[] = {
  198. "clk26m",
  199. "syspll_d2",
  200. "mmpll_d6",
  201. "syspll_d3",
  202. "mmpll_d7",
  203. "univpll_d3",
  204. "univpll_d2_d2",
  205. "syspll_d2_d2",
  206. "syspll_d3_d2",
  207. "univpll_d3_d2"
  208. };
  209. static const char * const dsp_parents[] = {
  210. "clk26m",
  211. "mmpll_d6",
  212. "mmpll_d7",
  213. "univpll_d3",
  214. "syspll_d3",
  215. "univpll_d2_d2",
  216. "syspll_d2_d2",
  217. "univpll_d3_d2",
  218. "syspll_d3_d2"
  219. };
  220. static const char * const dsp1_parents[] = {
  221. "clk26m",
  222. "mmpll_d6",
  223. "mmpll_d7",
  224. "univpll_d3",
  225. "syspll_d3",
  226. "univpll_d2_d2",
  227. "syspll_d2_d2",
  228. "univpll_d3_d2",
  229. "syspll_d3_d2"
  230. };
  231. static const char * const dsp2_parents[] = {
  232. "clk26m",
  233. "mmpll_d6",
  234. "mmpll_d7",
  235. "univpll_d3",
  236. "syspll_d3",
  237. "univpll_d2_d2",
  238. "syspll_d2_d2",
  239. "univpll_d3_d2",
  240. "syspll_d3_d2"
  241. };
  242. static const char * const ipu_if_parents[] = {
  243. "clk26m",
  244. "mmpll_d6",
  245. "mmpll_d7",
  246. "univpll_d3",
  247. "syspll_d3",
  248. "univpll_d2_d2",
  249. "syspll_d2_d2",
  250. "univpll_d3_d2",
  251. "syspll_d3_d2"
  252. };
  253. static const char * const mfg_parents[] = {
  254. "clk26m",
  255. "mfgpll_ck",
  256. "univpll_d3",
  257. "syspll_d3"
  258. };
  259. static const char * const f52m_mfg_parents[] = {
  260. "clk26m",
  261. "univpll_d3_d2",
  262. "univpll_d3_d4",
  263. "univpll_d3_d8"
  264. };
  265. static const char * const camtg_parents[] = {
  266. "clk26m",
  267. "univ_192m_d8",
  268. "univpll_d3_d8",
  269. "univ_192m_d4",
  270. "univpll_d3_d16",
  271. "csw_f26m_ck_d2",
  272. "univ_192m_d16",
  273. "univ_192m_d32"
  274. };
  275. static const char * const camtg2_parents[] = {
  276. "clk26m",
  277. "univ_192m_d8",
  278. "univpll_d3_d8",
  279. "univ_192m_d4",
  280. "univpll_d3_d16",
  281. "csw_f26m_ck_d2",
  282. "univ_192m_d16",
  283. "univ_192m_d32"
  284. };
  285. static const char * const camtg3_parents[] = {
  286. "clk26m",
  287. "univ_192m_d8",
  288. "univpll_d3_d8",
  289. "univ_192m_d4",
  290. "univpll_d3_d16",
  291. "csw_f26m_ck_d2",
  292. "univ_192m_d16",
  293. "univ_192m_d32"
  294. };
  295. static const char * const camtg4_parents[] = {
  296. "clk26m",
  297. "univ_192m_d8",
  298. "univpll_d3_d8",
  299. "univ_192m_d4",
  300. "univpll_d3_d16",
  301. "csw_f26m_ck_d2",
  302. "univ_192m_d16",
  303. "univ_192m_d32"
  304. };
  305. static const char * const uart_parents[] = {
  306. "clk26m",
  307. "univpll_d3_d8"
  308. };
  309. static const char * const spi_parents[] = {
  310. "clk26m",
  311. "syspll_d5_d2",
  312. "syspll_d3_d4",
  313. "msdcpll_d4"
  314. };
  315. static const char * const msdc50_hclk_parents[] = {
  316. "clk26m",
  317. "syspll_d2_d2",
  318. "syspll_d3_d2"
  319. };
  320. static const char * const msdc50_0_parents[] = {
  321. "clk26m",
  322. "msdcpll_ck",
  323. "msdcpll_d2",
  324. "univpll_d2_d4",
  325. "syspll_d3_d2",
  326. "univpll_d2_d2"
  327. };
  328. static const char * const msdc30_1_parents[] = {
  329. "clk26m",
  330. "univpll_d3_d2",
  331. "syspll_d3_d2",
  332. "syspll_d7",
  333. "msdcpll_d2"
  334. };
  335. static const char * const msdc30_2_parents[] = {
  336. "clk26m",
  337. "univpll_d3_d2",
  338. "syspll_d3_d2",
  339. "syspll_d7",
  340. "msdcpll_d2"
  341. };
  342. static const char * const audio_parents[] = {
  343. "clk26m",
  344. "syspll_d5_d4",
  345. "syspll_d7_d4",
  346. "syspll_d2_d16"
  347. };
  348. static const char * const aud_intbus_parents[] = {
  349. "clk26m",
  350. "syspll_d2_d4",
  351. "syspll_d7_d2"
  352. };
  353. static const char * const pmicspi_parents[] = {
  354. "clk26m",
  355. "syspll_d2_d8",
  356. "osc_d8"
  357. };
  358. static const char * const fpwrap_ulposc_parents[] = {
  359. "clk26m",
  360. "osc_d16",
  361. "osc_d4",
  362. "osc_d8"
  363. };
  364. static const char * const atb_parents[] = {
  365. "clk26m",
  366. "syspll_d2_d2",
  367. "syspll_d5"
  368. };
  369. static const char * const dpi0_parents[] = {
  370. "clk26m",
  371. "tvdpll_d2",
  372. "tvdpll_d4",
  373. "tvdpll_d8",
  374. "tvdpll_d16",
  375. "univpll_d5_d2",
  376. "univpll_d3_d4",
  377. "syspll_d3_d4",
  378. "univpll_d3_d8"
  379. };
  380. static const char * const scam_parents[] = {
  381. "clk26m",
  382. "syspll_d5_d2"
  383. };
  384. static const char * const disppwm_parents[] = {
  385. "clk26m",
  386. "univpll_d3_d4",
  387. "osc_d2",
  388. "osc_d4",
  389. "osc_d16"
  390. };
  391. static const char * const usb_top_parents[] = {
  392. "clk26m",
  393. "univpll_d5_d4",
  394. "univpll_d3_d4",
  395. "univpll_d5_d2"
  396. };
  397. static const char * const ssusb_top_xhci_parents[] = {
  398. "clk26m",
  399. "univpll_d5_d4",
  400. "univpll_d3_d4",
  401. "univpll_d5_d2"
  402. };
  403. static const char * const spm_parents[] = {
  404. "clk26m",
  405. "syspll_d2_d8"
  406. };
  407. static const char * const i2c_parents[] = {
  408. "clk26m",
  409. "syspll_d2_d8",
  410. "univpll_d5_d2"
  411. };
  412. static const char * const scp_parents[] = {
  413. "clk26m",
  414. "univpll_d2_d8",
  415. "syspll_d5",
  416. "syspll_d2_d2",
  417. "univpll_d2_d2",
  418. "syspll_d3",
  419. "univpll_d3"
  420. };
  421. static const char * const seninf_parents[] = {
  422. "clk26m",
  423. "univpll_d2_d2",
  424. "univpll_d3_d2",
  425. "univpll_d2_d4"
  426. };
  427. static const char * const dxcc_parents[] = {
  428. "clk26m",
  429. "syspll_d2_d2",
  430. "syspll_d2_d4",
  431. "syspll_d2_d8"
  432. };
  433. static const char * const aud_engen1_parents[] = {
  434. "clk26m",
  435. "apll1_d2",
  436. "apll1_d4",
  437. "apll1_d8"
  438. };
  439. static const char * const aud_engen2_parents[] = {
  440. "clk26m",
  441. "apll2_d2",
  442. "apll2_d4",
  443. "apll2_d8"
  444. };
  445. static const char * const faes_ufsfde_parents[] = {
  446. "clk26m",
  447. "syspll_d2",
  448. "syspll_d2_d2",
  449. "syspll_d3",
  450. "syspll_d2_d4",
  451. "univpll_d3"
  452. };
  453. static const char * const fufs_parents[] = {
  454. "clk26m",
  455. "syspll_d2_d4",
  456. "syspll_d2_d8",
  457. "syspll_d2_d16"
  458. };
  459. static const char * const aud_1_parents[] = {
  460. "clk26m",
  461. "apll1_ck"
  462. };
  463. static const char * const aud_2_parents[] = {
  464. "clk26m",
  465. "apll2_ck"
  466. };
  467. /*
  468. * CRITICAL CLOCK:
  469. * axi_sel is the main bus clock of whole SOC.
  470. * spm_sel is the clock of the always-on co-processor.
  471. */
  472. static const struct mtk_mux top_muxes[] = {
  473. /* CLK_CFG_0 */
  474. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
  475. axi_parents, 0x40,
  476. 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
  477. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
  478. mm_parents, 0x40,
  479. 0x44, 0x48, 8, 3, 15, 0x004, 1),
  480. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
  481. img_parents, 0x40,
  482. 0x44, 0x48, 16, 3, 23, 0x004, 2),
  483. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
  484. cam_parents, 0x40,
  485. 0x44, 0x48, 24, 4, 31, 0x004, 3),
  486. /* CLK_CFG_1 */
  487. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
  488. dsp_parents, 0x50,
  489. 0x54, 0x58, 0, 4, 7, 0x004, 4),
  490. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
  491. dsp1_parents, 0x50,
  492. 0x54, 0x58, 8, 4, 15, 0x004, 5),
  493. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
  494. dsp2_parents, 0x50,
  495. 0x54, 0x58, 16, 4, 23, 0x004, 6),
  496. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
  497. ipu_if_parents, 0x50,
  498. 0x54, 0x58, 24, 4, 31, 0x004, 7),
  499. /* CLK_CFG_2 */
  500. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
  501. mfg_parents, 0x60,
  502. 0x64, 0x68, 0, 2, 7, 0x004, 8),
  503. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
  504. f52m_mfg_parents, 0x60,
  505. 0x64, 0x68, 8, 2, 15, 0x004, 9),
  506. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
  507. camtg_parents, 0x60,
  508. 0x64, 0x68, 16, 3, 23, 0x004, 10),
  509. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
  510. camtg2_parents, 0x60,
  511. 0x64, 0x68, 24, 3, 31, 0x004, 11),
  512. /* CLK_CFG_3 */
  513. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
  514. camtg3_parents, 0x70,
  515. 0x74, 0x78, 0, 3, 7, 0x004, 12),
  516. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
  517. camtg4_parents, 0x70,
  518. 0x74, 0x78, 8, 3, 15, 0x004, 13),
  519. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
  520. uart_parents, 0x70,
  521. 0x74, 0x78, 16, 1, 23, 0x004, 14),
  522. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
  523. spi_parents, 0x70,
  524. 0x74, 0x78, 24, 2, 31, 0x004, 15),
  525. /* CLK_CFG_4 */
  526. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
  527. msdc50_hclk_parents, 0x80,
  528. 0x84, 0x88, 0, 2, 7, 0x004, 16),
  529. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
  530. msdc50_0_parents, 0x80,
  531. 0x84, 0x88, 8, 3, 15, 0x004, 17),
  532. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
  533. msdc30_1_parents, 0x80,
  534. 0x84, 0x88, 16, 3, 23, 0x004, 18),
  535. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
  536. msdc30_2_parents, 0x80,
  537. 0x84, 0x88, 24, 3, 31, 0x004, 19),
  538. /* CLK_CFG_5 */
  539. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
  540. audio_parents, 0x90,
  541. 0x94, 0x98, 0, 2, 7, 0x004, 20),
  542. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
  543. aud_intbus_parents, 0x90,
  544. 0x94, 0x98, 8, 2, 15, 0x004, 21),
  545. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
  546. pmicspi_parents, 0x90,
  547. 0x94, 0x98, 16, 2, 23, 0x004, 22),
  548. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
  549. fpwrap_ulposc_parents, 0x90,
  550. 0x94, 0x98, 24, 2, 31, 0x004, 23),
  551. /* CLK_CFG_6 */
  552. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
  553. atb_parents, 0xa0,
  554. 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
  555. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
  556. dpi0_parents, 0xa0,
  557. 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
  558. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
  559. scam_parents, 0xa0,
  560. 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
  561. /* CLK_CFG_7 */
  562. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
  563. disppwm_parents, 0xb0,
  564. 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
  565. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
  566. usb_top_parents, 0xb0,
  567. 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
  568. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
  569. ssusb_top_xhci_parents, 0xb0,
  570. 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
  571. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
  572. spm_parents, 0xb0,
  573. 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
  574. /* CLK_CFG_8 */
  575. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
  576. i2c_parents, 0xc0,
  577. 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
  578. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
  579. scp_parents, 0xc0,
  580. 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
  581. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
  582. seninf_parents, 0xc0,
  583. 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
  584. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
  585. dxcc_parents, 0xc0,
  586. 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
  587. /* CLK_CFG_9 */
  588. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
  589. aud_engen1_parents, 0xd0,
  590. 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
  591. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
  592. aud_engen2_parents, 0xd0,
  593. 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
  594. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
  595. faes_ufsfde_parents, 0xd0,
  596. 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
  597. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
  598. fufs_parents, 0xd0,
  599. 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
  600. /* CLK_CFG_10 */
  601. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
  602. aud_1_parents, 0xe0,
  603. 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
  604. MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
  605. aud_2_parents, 0xe0,
  606. 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
  607. };
  608. static const char * const apll_i2s0_parents[] = {
  609. "aud_1_sel",
  610. "aud_2_sel"
  611. };
  612. static const char * const apll_i2s1_parents[] = {
  613. "aud_1_sel",
  614. "aud_2_sel"
  615. };
  616. static const char * const apll_i2s2_parents[] = {
  617. "aud_1_sel",
  618. "aud_2_sel"
  619. };
  620. static const char * const apll_i2s3_parents[] = {
  621. "aud_1_sel",
  622. "aud_2_sel"
  623. };
  624. static const char * const apll_i2s4_parents[] = {
  625. "aud_1_sel",
  626. "aud_2_sel"
  627. };
  628. static const char * const apll_i2s5_parents[] = {
  629. "aud_1_sel",
  630. "aud_2_sel"
  631. };
  632. static struct mtk_composite top_aud_muxes[] = {
  633. MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
  634. 0x320, 8, 1),
  635. MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
  636. 0x320, 9, 1),
  637. MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
  638. 0x320, 10, 1),
  639. MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
  640. 0x320, 11, 1),
  641. MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
  642. 0x320, 12, 1),
  643. MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
  644. 0x328, 20, 1),
  645. };
  646. static const char * const mcu_mp0_parents[] = {
  647. "clk26m",
  648. "armpll_ll",
  649. "armpll_div_pll1",
  650. "armpll_div_pll2"
  651. };
  652. static const char * const mcu_mp2_parents[] = {
  653. "clk26m",
  654. "armpll_l",
  655. "armpll_div_pll1",
  656. "armpll_div_pll2"
  657. };
  658. static const char * const mcu_bus_parents[] = {
  659. "clk26m",
  660. "ccipll",
  661. "armpll_div_pll1",
  662. "armpll_div_pll2"
  663. };
  664. static struct mtk_composite mcu_muxes[] = {
  665. /* mp0_pll_divider_cfg */
  666. MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
  667. /* mp2_pll_divider_cfg */
  668. MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
  669. /* bus_pll_divider_cfg */
  670. MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
  671. };
  672. static struct mtk_composite top_aud_divs[] = {
  673. DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
  674. 0x320, 2, 0x324, 8, 0),
  675. DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
  676. 0x320, 3, 0x324, 8, 8),
  677. DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel",
  678. 0x320, 4, 0x324, 8, 16),
  679. DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel",
  680. 0x320, 5, 0x324, 8, 24),
  681. DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
  682. 0x320, 6, 0x328, 8, 0),
  683. DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
  684. 0x320, 7, 0x328, 8, 8),
  685. };
  686. static const struct mtk_gate_regs top_cg_regs = {
  687. .set_ofs = 0x104,
  688. .clr_ofs = 0x104,
  689. .sta_ofs = 0x104,
  690. };
  691. #define GATE_TOP(_id, _name, _parent, _shift) \
  692. GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
  693. &mtk_clk_gate_ops_no_setclr_inv)
  694. static const struct mtk_gate top_clks[] = {
  695. /* TOP */
  696. GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
  697. GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
  698. };
  699. static const struct mtk_gate_regs infra0_cg_regs = {
  700. .set_ofs = 0x80,
  701. .clr_ofs = 0x84,
  702. .sta_ofs = 0x90,
  703. };
  704. static const struct mtk_gate_regs infra1_cg_regs = {
  705. .set_ofs = 0x88,
  706. .clr_ofs = 0x8c,
  707. .sta_ofs = 0x94,
  708. };
  709. static const struct mtk_gate_regs infra2_cg_regs = {
  710. .set_ofs = 0xa4,
  711. .clr_ofs = 0xa8,
  712. .sta_ofs = 0xac,
  713. };
  714. static const struct mtk_gate_regs infra3_cg_regs = {
  715. .set_ofs = 0xc0,
  716. .clr_ofs = 0xc4,
  717. .sta_ofs = 0xc8,
  718. };
  719. #define GATE_INFRA0(_id, _name, _parent, _shift) \
  720. GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
  721. &mtk_clk_gate_ops_setclr)
  722. #define GATE_INFRA1(_id, _name, _parent, _shift) \
  723. GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
  724. &mtk_clk_gate_ops_setclr)
  725. #define GATE_INFRA2(_id, _name, _parent, _shift) \
  726. GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
  727. &mtk_clk_gate_ops_setclr)
  728. #define GATE_INFRA3(_id, _name, _parent, _shift) \
  729. GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
  730. &mtk_clk_gate_ops_setclr)
  731. static const struct mtk_gate infra_clks[] = {
  732. /* INFRA0 */
  733. GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
  734. "axi_sel", 0),
  735. GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
  736. "axi_sel", 1),
  737. GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
  738. "axi_sel", 2),
  739. GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
  740. "axi_sel", 3),
  741. GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
  742. "scp_sel", 4),
  743. GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
  744. "f_f26m_ck", 5),
  745. GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
  746. "axi_sel", 6),
  747. GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
  748. "axi_sel", 8),
  749. GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
  750. "axi_sel", 9),
  751. GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
  752. "axi_sel", 10),
  753. GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
  754. "i2c_sel", 11),
  755. GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
  756. "i2c_sel", 12),
  757. GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
  758. "i2c_sel", 13),
  759. GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
  760. "i2c_sel", 14),
  761. GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
  762. "axi_sel", 15),
  763. GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
  764. "i2c_sel", 16),
  765. GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
  766. "i2c_sel", 17),
  767. GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
  768. "i2c_sel", 18),
  769. GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
  770. "i2c_sel", 19),
  771. GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
  772. "i2c_sel", 21),
  773. GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
  774. "uart_sel", 22),
  775. GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
  776. "uart_sel", 23),
  777. GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
  778. "uart_sel", 24),
  779. GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
  780. "uart_sel", 25),
  781. GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
  782. "axi_sel", 27),
  783. GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
  784. "axi_sel", 28),
  785. GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
  786. "axi_sel", 31),
  787. /* INFRA1 */
  788. GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
  789. "spi_sel", 1),
  790. GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
  791. "msdc50_hclk_sel", 2),
  792. GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
  793. "axi_sel", 4),
  794. GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
  795. "axi_sel", 5),
  796. GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
  797. "msdc50_0_sel", 6),
  798. GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
  799. "f_f26m_ck", 7),
  800. GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
  801. "axi_sel", 8),
  802. GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
  803. "axi_sel", 9),
  804. GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
  805. "f_f26m_ck", 10),
  806. GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
  807. "axi_sel", 11),
  808. GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
  809. "axi_sel", 12),
  810. GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
  811. "axi_sel", 13),
  812. GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
  813. "f_f26m_ck", 14),
  814. GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
  815. "msdc30_1_sel", 16),
  816. GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
  817. "msdc30_2_sel", 17),
  818. GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
  819. "axi_sel", 18),
  820. GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
  821. "axi_sel", 19),
  822. GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
  823. "axi_sel", 20),
  824. GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
  825. "axi_sel", 23),
  826. GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
  827. "axi_sel", 24),
  828. GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio",
  829. "axi_sel", 25),
  830. GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
  831. "axi_sel", 26),
  832. GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
  833. "dxcc_sel", 27),
  834. GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
  835. "dxcc_sel", 28),
  836. GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
  837. "axi_sel", 30),
  838. GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
  839. "f_f26m_ck", 31),
  840. /* INFRA2 */
  841. GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
  842. "f_f26m_ck", 0),
  843. GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
  844. "usb_top_sel", 1),
  845. GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
  846. "axi_sel", 2),
  847. GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk",
  848. "axi_sel", 3),
  849. GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk",
  850. "f_f26m_ck", 4),
  851. GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
  852. "spi_sel", 6),
  853. GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
  854. "i2c_sel", 7),
  855. GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
  856. "f_f26m_ck", 8),
  857. GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
  858. "spi_sel", 9),
  859. GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
  860. "spi_sel", 10),
  861. GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
  862. "ssusb_top_xhci_sel", 11),
  863. GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
  864. "fufs_sel", 12),
  865. GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
  866. "fufs_sel", 13),
  867. GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
  868. "axi_sel", 14),
  869. GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
  870. "axi_sel", 16),
  871. GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
  872. "i2c_sel", 18),
  873. GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
  874. "i2c_sel", 19),
  875. GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
  876. "i2c_sel", 20),
  877. GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
  878. "i2c_sel", 21),
  879. GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
  880. "i2c_sel", 22),
  881. GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
  882. "i2c_sel", 23),
  883. GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
  884. "i2c_sel", 24),
  885. GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
  886. "spi_sel", 25),
  887. GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
  888. "spi_sel", 26),
  889. GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
  890. "axi_sel", 27),
  891. GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
  892. "fufs_sel", 28),
  893. GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
  894. "faes_ufsfde_sel", 29),
  895. GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
  896. "fufs_sel", 30),
  897. /* INFRA3 */
  898. GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
  899. "msdc50_0_sel", 0),
  900. GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
  901. "msdc50_0_sel", 1),
  902. GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
  903. "msdc50_0_sel", 2),
  904. GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
  905. "axi_sel", 5),
  906. GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
  907. "i2c_sel", 6),
  908. GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
  909. "msdc50_hclk_sel", 7),
  910. GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
  911. "msdc50_hclk_sel", 8),
  912. GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
  913. "axi_sel", 16),
  914. GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
  915. "axi_sel", 17),
  916. GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
  917. "axi_sel", 18),
  918. GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
  919. "axi_sel", 19),
  920. GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
  921. "f_f26m_ck", 20),
  922. GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
  923. "axi_sel", 21),
  924. GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
  925. "i2c_sel", 22),
  926. GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
  927. "i2c_sel", 23),
  928. GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
  929. "msdc50_0_sel", 24),
  930. };
  931. static const struct mtk_gate_regs peri_cg_regs = {
  932. .set_ofs = 0x20c,
  933. .clr_ofs = 0x20c,
  934. .sta_ofs = 0x20c,
  935. };
  936. #define GATE_PERI(_id, _name, _parent, _shift) \
  937. GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
  938. &mtk_clk_gate_ops_no_setclr_inv)
  939. static const struct mtk_gate peri_clks[] = {
  940. GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
  941. };
  942. static const struct mtk_gate_regs apmixed_cg_regs = {
  943. .set_ofs = 0x20,
  944. .clr_ofs = 0x20,
  945. .sta_ofs = 0x20,
  946. };
  947. #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
  948. GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
  949. _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
  950. #define GATE_APMIXED(_id, _name, _parent, _shift) \
  951. GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
  952. /*
  953. * CRITICAL CLOCK:
  954. * apmixed_appll26m is the toppest clock gate of all PLLs.
  955. */
  956. static const struct mtk_gate apmixed_clks[] = {
  957. /* AUDIO0 */
  958. GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
  959. "f_f26m_ck", 4),
  960. GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
  961. "f_f26m_ck", 5, CLK_IS_CRITICAL),
  962. GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
  963. "f_f26m_ck", 6),
  964. GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
  965. "f_f26m_ck", 7),
  966. GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
  967. "f_f26m_ck", 8),
  968. GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
  969. "f_f26m_ck", 9),
  970. GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
  971. "f_f26m_ck", 11),
  972. GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
  973. "f_f26m_ck", 13),
  974. GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
  975. "f_f26m_ck", 14),
  976. GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
  977. "f_f26m_ck", 16),
  978. GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
  979. "f_f26m_ck", 17),
  980. };
  981. #define MT8183_PLL_FMAX (3800UL * MHZ)
  982. #define MT8183_PLL_FMIN (1500UL * MHZ)
  983. #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  984. _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
  985. _pd_shift, _tuner_reg, _tuner_en_reg, \
  986. _tuner_en_bit, _pcw_reg, _pcw_shift, \
  987. _pcw_chg_reg, _div_table) { \
  988. .id = _id, \
  989. .name = _name, \
  990. .reg = _reg, \
  991. .pwr_reg = _pwr_reg, \
  992. .en_mask = _en_mask, \
  993. .flags = _flags, \
  994. .rst_bar_mask = _rst_bar_mask, \
  995. .fmax = MT8183_PLL_FMAX, \
  996. .fmin = MT8183_PLL_FMIN, \
  997. .pcwbits = _pcwbits, \
  998. .pcwibits = _pcwibits, \
  999. .pd_reg = _pd_reg, \
  1000. .pd_shift = _pd_shift, \
  1001. .tuner_reg = _tuner_reg, \
  1002. .tuner_en_reg = _tuner_en_reg, \
  1003. .tuner_en_bit = _tuner_en_bit, \
  1004. .pcw_reg = _pcw_reg, \
  1005. .pcw_shift = _pcw_shift, \
  1006. .pcw_chg_reg = _pcw_chg_reg, \
  1007. .div_table = _div_table, \
  1008. }
  1009. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  1010. _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
  1011. _pd_shift, _tuner_reg, _tuner_en_reg, \
  1012. _tuner_en_bit, _pcw_reg, _pcw_shift, \
  1013. _pcw_chg_reg) \
  1014. PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  1015. _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
  1016. _pd_shift, _tuner_reg, _tuner_en_reg, \
  1017. _tuner_en_bit, _pcw_reg, _pcw_shift, \
  1018. _pcw_chg_reg, NULL)
  1019. static const struct mtk_pll_div_table armpll_div_table[] = {
  1020. { .div = 0, .freq = MT8183_PLL_FMAX },
  1021. { .div = 1, .freq = 1500 * MHZ },
  1022. { .div = 2, .freq = 750 * MHZ },
  1023. { .div = 3, .freq = 375 * MHZ },
  1024. { .div = 4, .freq = 187500000 },
  1025. { } /* sentinel */
  1026. };
  1027. static const struct mtk_pll_div_table mfgpll_div_table[] = {
  1028. { .div = 0, .freq = MT8183_PLL_FMAX },
  1029. { .div = 1, .freq = 1600 * MHZ },
  1030. { .div = 2, .freq = 800 * MHZ },
  1031. { .div = 3, .freq = 400 * MHZ },
  1032. { .div = 4, .freq = 200 * MHZ },
  1033. { } /* sentinel */
  1034. };
  1035. static const struct mtk_pll_data plls[] = {
  1036. PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
  1037. HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
  1038. 0x0204, 0, 0, armpll_div_table),
  1039. PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
  1040. HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
  1041. 0x0214, 0, 0, armpll_div_table),
  1042. PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
  1043. HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
  1044. 0x0294, 0, 0),
  1045. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
  1046. HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
  1047. 0x0224, 0, 0),
  1048. PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
  1049. HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
  1050. 0x0234, 0, 0),
  1051. PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
  1052. 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
  1053. mfgpll_div_table),
  1054. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
  1055. 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
  1056. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
  1057. 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
  1058. PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
  1059. HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
  1060. 0x0274, 0, 0),
  1061. PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
  1062. 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
  1063. PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
  1064. 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
  1065. };
  1066. static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
  1067. {
  1068. struct clk_onecell_data *clk_data;
  1069. struct device_node *node = pdev->dev.of_node;
  1070. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
  1071. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  1072. mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
  1073. clk_data);
  1074. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1075. }
  1076. static struct clk_onecell_data *top_clk_data;
  1077. static void clk_mt8183_top_init_early(struct device_node *node)
  1078. {
  1079. int i;
  1080. top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
  1081. for (i = 0; i < CLK_TOP_NR_CLK; i++)
  1082. top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
  1083. mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
  1084. top_clk_data);
  1085. of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
  1086. }
  1087. CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
  1088. clk_mt8183_top_init_early);
  1089. static int clk_mt8183_top_probe(struct platform_device *pdev)
  1090. {
  1091. void __iomem *base;
  1092. struct device_node *node = pdev->dev.of_node;
  1093. base = devm_platform_ioremap_resource(pdev, 0);
  1094. if (IS_ERR(base))
  1095. return PTR_ERR(base);
  1096. mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  1097. top_clk_data);
  1098. mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
  1099. top_clk_data);
  1100. mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
  1101. mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
  1102. node, &mt8183_clk_lock, top_clk_data);
  1103. mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
  1104. base, &mt8183_clk_lock, top_clk_data);
  1105. mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
  1106. base, &mt8183_clk_lock, top_clk_data);
  1107. mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  1108. top_clk_data);
  1109. return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
  1110. }
  1111. static int clk_mt8183_infra_probe(struct platform_device *pdev)
  1112. {
  1113. struct clk_onecell_data *clk_data;
  1114. struct device_node *node = pdev->dev.of_node;
  1115. int r;
  1116. clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  1117. mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  1118. clk_data);
  1119. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1120. if (r) {
  1121. dev_err(&pdev->dev,
  1122. "%s(): could not register clock provider: %d\n",
  1123. __func__, r);
  1124. return r;
  1125. }
  1126. mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
  1127. return r;
  1128. }
  1129. static int clk_mt8183_peri_probe(struct platform_device *pdev)
  1130. {
  1131. struct clk_onecell_data *clk_data;
  1132. struct device_node *node = pdev->dev.of_node;
  1133. clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
  1134. mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  1135. clk_data);
  1136. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1137. }
  1138. static int clk_mt8183_mcu_probe(struct platform_device *pdev)
  1139. {
  1140. struct clk_onecell_data *clk_data;
  1141. struct device_node *node = pdev->dev.of_node;
  1142. void __iomem *base;
  1143. base = devm_platform_ioremap_resource(pdev, 0);
  1144. if (IS_ERR(base))
  1145. return PTR_ERR(base);
  1146. clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
  1147. mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
  1148. &mt8183_clk_lock, clk_data);
  1149. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1150. }
  1151. static const struct of_device_id of_match_clk_mt8183[] = {
  1152. {
  1153. .compatible = "mediatek,mt8183-apmixedsys",
  1154. .data = clk_mt8183_apmixed_probe,
  1155. }, {
  1156. .compatible = "mediatek,mt8183-topckgen",
  1157. .data = clk_mt8183_top_probe,
  1158. }, {
  1159. .compatible = "mediatek,mt8183-infracfg",
  1160. .data = clk_mt8183_infra_probe,
  1161. }, {
  1162. .compatible = "mediatek,mt8183-pericfg",
  1163. .data = clk_mt8183_peri_probe,
  1164. }, {
  1165. .compatible = "mediatek,mt8183-mcucfg",
  1166. .data = clk_mt8183_mcu_probe,
  1167. }, {
  1168. /* sentinel */
  1169. }
  1170. };
  1171. static int clk_mt8183_probe(struct platform_device *pdev)
  1172. {
  1173. int (*clk_probe)(struct platform_device *pdev);
  1174. int r;
  1175. clk_probe = of_device_get_match_data(&pdev->dev);
  1176. if (!clk_probe)
  1177. return -EINVAL;
  1178. r = clk_probe(pdev);
  1179. if (r)
  1180. dev_err(&pdev->dev,
  1181. "could not register clock provider: %s: %d\n",
  1182. pdev->name, r);
  1183. return r;
  1184. }
  1185. static struct platform_driver clk_mt8183_drv = {
  1186. .probe = clk_mt8183_probe,
  1187. .driver = {
  1188. .name = "clk-mt8183",
  1189. .of_match_table = of_match_clk_mt8183,
  1190. },
  1191. };
  1192. static int __init clk_mt8183_init(void)
  1193. {
  1194. return platform_driver_register(&clk_mt8183_drv);
  1195. }
  1196. arch_initcall(clk_mt8183_init);