clk-mt8183-venc.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. #include <linux/clk-provider.h>
  6. #include <linux/platform_device.h>
  7. #include "clk-mtk.h"
  8. #include "clk-gate.h"
  9. #include <dt-bindings/clock/mt8183-clk.h>
  10. static const struct mtk_gate_regs venc_cg_regs = {
  11. .set_ofs = 0x4,
  12. .clr_ofs = 0x8,
  13. .sta_ofs = 0x0,
  14. };
  15. #define GATE_VENC_I(_id, _name, _parent, _shift) \
  16. GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
  17. &mtk_clk_gate_ops_setclr_inv)
  18. static const struct mtk_gate venc_clks[] = {
  19. GATE_VENC_I(CLK_VENC_LARB, "venc_larb",
  20. "mm_sel", 0),
  21. GATE_VENC_I(CLK_VENC_VENC, "venc_venc",
  22. "mm_sel", 4),
  23. GATE_VENC_I(CLK_VENC_JPGENC, "venc_jpgenc",
  24. "mm_sel", 8),
  25. };
  26. static int clk_mt8183_venc_probe(struct platform_device *pdev)
  27. {
  28. struct clk_onecell_data *clk_data;
  29. struct device_node *node = pdev->dev.of_node;
  30. clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
  31. mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
  32. clk_data);
  33. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  34. }
  35. static const struct of_device_id of_match_clk_mt8183_venc[] = {
  36. { .compatible = "mediatek,mt8183-vencsys", },
  37. {}
  38. };
  39. static struct platform_driver clk_mt8183_venc_drv = {
  40. .probe = clk_mt8183_venc_probe,
  41. .driver = {
  42. .name = "clk-mt8183-venc",
  43. .of_match_table = of_match_clk_mt8183_venc,
  44. },
  45. };
  46. builtin_platform_driver(clk_mt8183_venc_drv);