clk-mt8183-mm.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106
  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. #include <linux/clk-provider.h>
  6. #include <linux/platform_device.h>
  7. #include "clk-mtk.h"
  8. #include "clk-gate.h"
  9. #include <dt-bindings/clock/mt8183-clk.h>
  10. static const struct mtk_gate_regs mm0_cg_regs = {
  11. .set_ofs = 0x104,
  12. .clr_ofs = 0x108,
  13. .sta_ofs = 0x100,
  14. };
  15. static const struct mtk_gate_regs mm1_cg_regs = {
  16. .set_ofs = 0x114,
  17. .clr_ofs = 0x118,
  18. .sta_ofs = 0x110,
  19. };
  20. #define GATE_MM0(_id, _name, _parent, _shift) \
  21. GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
  22. &mtk_clk_gate_ops_setclr)
  23. #define GATE_MM1(_id, _name, _parent, _shift) \
  24. GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
  25. &mtk_clk_gate_ops_setclr)
  26. static const struct mtk_gate mm_clks[] = {
  27. /* MM0 */
  28. GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
  29. GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
  30. GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
  31. GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
  32. GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
  33. GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
  34. GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
  35. GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
  36. GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
  37. GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
  38. GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
  39. GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
  40. GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
  41. GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
  42. GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
  43. GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
  44. GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
  45. GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
  46. GATE_MM0(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 18),
  47. GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
  48. GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
  49. GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
  50. GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
  51. GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
  52. GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
  53. GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
  54. GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
  55. GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
  56. GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
  57. GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
  58. GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
  59. GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
  60. /* MM1 */
  61. GATE_MM1(CLK_MM_DSI0_MM, "mm_dsi0_mm", "mm_sel", 0),
  62. GATE_MM1(CLK_MM_DSI0_IF, "mm_dsi0_if", "mm_sel", 1),
  63. GATE_MM1(CLK_MM_DPI_MM, "mm_dpi_mm", "mm_sel", 2),
  64. GATE_MM1(CLK_MM_DPI_IF, "mm_dpi_if", "dpi0_sel", 3),
  65. GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
  66. GATE_MM1(CLK_MM_MDP_DL_RX, "mm_mdp_dl_rx", "mm_sel", 5),
  67. GATE_MM1(CLK_MM_IPU_DL_RX, "mm_ipu_dl_rx", "mm_sel", 6),
  68. GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
  69. GATE_MM1(CLK_MM_MMSYS_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
  70. GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
  71. GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
  72. GATE_MM1(CLK_MM_MDP_CCORR, "mm_mdp_ccorr", "mm_sel", 11),
  73. GATE_MM1(CLK_MM_DBI_MM, "mm_dbi_mm", "mm_sel", 12),
  74. GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13),
  75. };
  76. static int clk_mt8183_mm_probe(struct platform_device *pdev)
  77. {
  78. struct device *dev = &pdev->dev;
  79. struct device_node *node = dev->parent->of_node;
  80. struct clk_onecell_data *clk_data;
  81. clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
  82. mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
  83. clk_data);
  84. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  85. }
  86. static struct platform_driver clk_mt8183_mm_drv = {
  87. .probe = clk_mt8183_mm_probe,
  88. .driver = {
  89. .name = "clk-mt8183-mm",
  90. },
  91. };
  92. builtin_platform_driver(clk_mt8183_mm_drv);