clk-mt8183-ipu_adl.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. #include <linux/clk-provider.h>
  6. #include <linux/platform_device.h>
  7. #include "clk-mtk.h"
  8. #include "clk-gate.h"
  9. #include <dt-bindings/clock/mt8183-clk.h>
  10. static const struct mtk_gate_regs ipu_adl_cg_regs = {
  11. .set_ofs = 0x204,
  12. .clr_ofs = 0x204,
  13. .sta_ofs = 0x204,
  14. };
  15. #define GATE_IPU_ADL_I(_id, _name, _parent, _shift) \
  16. GATE_MTK(_id, _name, _parent, &ipu_adl_cg_regs, _shift, \
  17. &mtk_clk_gate_ops_no_setclr_inv)
  18. static const struct mtk_gate ipu_adl_clks[] = {
  19. GATE_IPU_ADL_I(CLK_IPU_ADL_CABGEN, "ipu_adl_cabgen", "dsp_sel", 24),
  20. };
  21. static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
  22. {
  23. struct clk_onecell_data *clk_data;
  24. struct device_node *node = pdev->dev.of_node;
  25. clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
  26. mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
  27. clk_data);
  28. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  29. }
  30. static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
  31. { .compatible = "mediatek,mt8183-ipu_adl", },
  32. {}
  33. };
  34. static struct platform_driver clk_mt8183_ipu_adl_drv = {
  35. .probe = clk_mt8183_ipu_adl_probe,
  36. .driver = {
  37. .name = "clk-mt8183-ipu_adl",
  38. .of_match_table = of_match_clk_mt8183_ipu_adl,
  39. },
  40. };
  41. builtin_platform_driver(clk_mt8183_ipu_adl_drv);