clk-mt8183-ipu1.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. #include <linux/clk-provider.h>
  6. #include <linux/platform_device.h>
  7. #include "clk-mtk.h"
  8. #include "clk-gate.h"
  9. #include <dt-bindings/clock/mt8183-clk.h>
  10. static const struct mtk_gate_regs ipu_core1_cg_regs = {
  11. .set_ofs = 0x4,
  12. .clr_ofs = 0x8,
  13. .sta_ofs = 0x0,
  14. };
  15. #define GATE_IPU_CORE1(_id, _name, _parent, _shift) \
  16. GATE_MTK(_id, _name, _parent, &ipu_core1_cg_regs, _shift, \
  17. &mtk_clk_gate_ops_setclr)
  18. static const struct mtk_gate ipu_core1_clks[] = {
  19. GATE_IPU_CORE1(CLK_IPU_CORE1_JTAG, "ipu_core1_jtag", "dsp_sel", 0),
  20. GATE_IPU_CORE1(CLK_IPU_CORE1_AXI, "ipu_core1_axi", "dsp_sel", 1),
  21. GATE_IPU_CORE1(CLK_IPU_CORE1_IPU, "ipu_core1_ipu", "dsp_sel", 2),
  22. };
  23. static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
  24. {
  25. struct clk_onecell_data *clk_data;
  26. struct device_node *node = pdev->dev.of_node;
  27. clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK);
  28. mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks),
  29. clk_data);
  30. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  31. }
  32. static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {
  33. { .compatible = "mediatek,mt8183-ipu_core1", },
  34. {}
  35. };
  36. static struct platform_driver clk_mt8183_ipu_core1_drv = {
  37. .probe = clk_mt8183_ipu_core1_probe,
  38. .driver = {
  39. .name = "clk-mt8183-ipu_core1",
  40. .of_match_table = of_match_clk_mt8183_ipu_core1,
  41. },
  42. };
  43. builtin_platform_driver(clk_mt8183_ipu_core1_drv);