clk-mt8183-img.c 1.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. #include <linux/clk-provider.h>
  6. #include <linux/platform_device.h>
  7. #include "clk-mtk.h"
  8. #include "clk-gate.h"
  9. #include <dt-bindings/clock/mt8183-clk.h>
  10. static const struct mtk_gate_regs img_cg_regs = {
  11. .set_ofs = 0x4,
  12. .clr_ofs = 0x8,
  13. .sta_ofs = 0x0,
  14. };
  15. #define GATE_IMG(_id, _name, _parent, _shift) \
  16. GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
  17. &mtk_clk_gate_ops_setclr)
  18. static const struct mtk_gate img_clks[] = {
  19. GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
  20. GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
  21. GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
  22. GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
  23. GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
  24. GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
  25. GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
  26. GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
  27. GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
  28. GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
  29. };
  30. static int clk_mt8183_img_probe(struct platform_device *pdev)
  31. {
  32. struct clk_onecell_data *clk_data;
  33. struct device_node *node = pdev->dev.of_node;
  34. clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
  35. mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
  36. clk_data);
  37. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  38. }
  39. static const struct of_device_id of_match_clk_mt8183_img[] = {
  40. { .compatible = "mediatek,mt8183-imgsys", },
  41. {}
  42. };
  43. static struct platform_driver clk_mt8183_img_drv = {
  44. .probe = clk_mt8183_img_probe,
  45. .driver = {
  46. .name = "clk-mt8183-img",
  47. .of_match_table = of_match_clk_mt8183_img,
  48. },
  49. };
  50. builtin_platform_driver(clk_mt8183_img_drv);