clk-mt8183-audio.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (c) 2018 MediaTek Inc.
  4. // Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. #include <linux/clk-provider.h>
  6. #include <linux/of_platform.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt8183-clk.h>
  11. static const struct mtk_gate_regs audio0_cg_regs = {
  12. .set_ofs = 0x0,
  13. .clr_ofs = 0x0,
  14. .sta_ofs = 0x0,
  15. };
  16. static const struct mtk_gate_regs audio1_cg_regs = {
  17. .set_ofs = 0x4,
  18. .clr_ofs = 0x4,
  19. .sta_ofs = 0x4,
  20. };
  21. #define GATE_AUDIO0(_id, _name, _parent, _shift) \
  22. GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
  23. &mtk_clk_gate_ops_no_setclr)
  24. #define GATE_AUDIO1(_id, _name, _parent, _shift) \
  25. GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
  26. &mtk_clk_gate_ops_no_setclr)
  27. static const struct mtk_gate audio_clks[] = {
  28. /* AUDIO0 */
  29. GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_sel",
  30. 2),
  31. GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_eng1_sel",
  32. 8),
  33. GATE_AUDIO0(CLK_AUDIO_24M, "aud_24m", "aud_eng2_sel",
  34. 9),
  35. GATE_AUDIO0(CLK_AUDIO_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
  36. 18),
  37. GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
  38. 19),
  39. GATE_AUDIO0(CLK_AUDIO_TDM, "aud_tdm", "apll12_divb",
  40. 20),
  41. GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_sel",
  42. 24),
  43. GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_sel",
  44. 25),
  45. GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", "audio_sel",
  46. 26),
  47. GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_sel",
  48. 27),
  49. /* AUDIO1 */
  50. GATE_AUDIO1(CLK_AUDIO_I2S1, "aud_i2s1", "audio_sel",
  51. 4),
  52. GATE_AUDIO1(CLK_AUDIO_I2S2, "aud_i2s2", "audio_sel",
  53. 5),
  54. GATE_AUDIO1(CLK_AUDIO_I2S3, "aud_i2s3", "audio_sel",
  55. 6),
  56. GATE_AUDIO1(CLK_AUDIO_I2S4, "aud_i2s4", "audio_sel",
  57. 7),
  58. GATE_AUDIO1(CLK_AUDIO_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
  59. 20),
  60. };
  61. static int clk_mt8183_audio_probe(struct platform_device *pdev)
  62. {
  63. struct clk_onecell_data *clk_data;
  64. int r;
  65. struct device_node *node = pdev->dev.of_node;
  66. clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
  67. mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
  68. clk_data);
  69. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  70. if (r)
  71. return r;
  72. r = devm_of_platform_populate(&pdev->dev);
  73. if (r)
  74. of_clk_del_provider(node);
  75. return r;
  76. }
  77. static const struct of_device_id of_match_clk_mt8183_audio[] = {
  78. { .compatible = "mediatek,mt8183-audiosys", },
  79. {}
  80. };
  81. static struct platform_driver clk_mt8183_audio_drv = {
  82. .probe = clk_mt8183_audio_probe,
  83. .driver = {
  84. .name = "clk-mt8183-audio",
  85. .of_match_table = of_match_clk_mt8183_audio,
  86. },
  87. };
  88. builtin_platform_driver(clk_mt8183_audio_drv);