clk-mt8167.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020 MediaTek Inc.
  4. * Copyright (c) 2020 BayLibre, SAS
  5. * Author: James Liao <jamesjj.liao@mediatek.com>
  6. * Fabien Parent <fparent@baylibre.com>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/slab.h>
  12. #include <linux/mfd/syscon.h>
  13. #include "clk-mtk.h"
  14. #include "clk-gate.h"
  15. #include <dt-bindings/clock/mt8167-clk.h>
  16. static DEFINE_SPINLOCK(mt8167_clk_lock);
  17. static const struct mtk_fixed_clk fixed_clks[] __initconst = {
  18. FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
  19. FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
  20. FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
  21. FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 75000000),
  22. FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
  23. FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000),
  24. };
  25. static const struct mtk_fixed_factor top_divs[] __initconst = {
  26. FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
  27. FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
  28. FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
  29. FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
  30. FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
  31. FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
  32. FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
  33. FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
  34. FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
  35. FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
  36. FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
  37. FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
  38. FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
  39. FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
  40. FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
  41. FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
  42. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  43. FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
  44. FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
  45. FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
  46. FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  47. FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
  48. FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
  49. FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
  50. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  51. FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
  52. FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
  53. FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  54. FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
  55. FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1),
  56. FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
  57. FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
  58. FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
  59. FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
  60. FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
  61. FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
  62. FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
  63. FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
  64. FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
  65. FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
  66. FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
  67. FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
  68. FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
  69. FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
  70. FACTOR(CLK_TOP_MIPI_26M, "mipi_26m", "clk26m", 1, 1),
  71. FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
  72. FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
  73. FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
  74. FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
  75. FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
  76. FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
  77. FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
  78. FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
  79. };
  80. static const char * const uart0_parents[] __initconst = {
  81. "clk26m_ck",
  82. "univpll_d24"
  83. };
  84. static const char * const gfmux_emi1x_parents[] __initconst = {
  85. "clk26m_ck",
  86. "dmpll_ck"
  87. };
  88. static const char * const emi_ddrphy_parents[] __initconst = {
  89. "gfmux_emi1x_sel",
  90. "gfmux_emi1x_sel"
  91. };
  92. static const char * const ahb_infra_parents[] __initconst = {
  93. "clk_null",
  94. "clk26m_ck",
  95. "mainpll_d11",
  96. "clk_null",
  97. "mainpll_d12",
  98. "clk_null",
  99. "clk_null",
  100. "clk_null",
  101. "clk_null",
  102. "clk_null",
  103. "clk_null",
  104. "clk_null",
  105. "mainpll_d10"
  106. };
  107. static const char * const csw_mux_mfg_parents[] __initconst = {
  108. "clk_null",
  109. "clk_null",
  110. "univpll_d3",
  111. "univpll_d2",
  112. "clk26m_ck",
  113. "mainpll_d4",
  114. "univpll_d24",
  115. "mmpll380m"
  116. };
  117. static const char * const msdc0_parents[] __initconst = {
  118. "clk26m_ck",
  119. "univpll_d6",
  120. "mainpll_d8",
  121. "univpll_d8",
  122. "mainpll_d16",
  123. "mmpll_200m",
  124. "mainpll_d12",
  125. "mmpll_d2"
  126. };
  127. static const char * const camtg_mm_parents[] __initconst = {
  128. "clk_null",
  129. "clk26m_ck",
  130. "usb_phy48m_ck",
  131. "clk_null",
  132. "univpll_d6"
  133. };
  134. static const char * const pwm_mm_parents[] __initconst = {
  135. "clk26m_ck",
  136. "univpll_d12"
  137. };
  138. static const char * const uart1_parents[] __initconst = {
  139. "clk26m_ck",
  140. "univpll_d24"
  141. };
  142. static const char * const msdc1_parents[] __initconst = {
  143. "clk26m_ck",
  144. "univpll_d6",
  145. "mainpll_d8",
  146. "univpll_d8",
  147. "mainpll_d16",
  148. "mmpll_200m",
  149. "mainpll_d12",
  150. "mmpll_d2"
  151. };
  152. static const char * const spm_52m_parents[] __initconst = {
  153. "clk26m_ck",
  154. "univpll_d24"
  155. };
  156. static const char * const pmicspi_parents[] __initconst = {
  157. "univpll_d20",
  158. "usb_phy48m_ck",
  159. "univpll_d16",
  160. "clk26m_ck"
  161. };
  162. static const char * const qaxi_aud26m_parents[] __initconst = {
  163. "clk26m_ck",
  164. "ahb_infra_sel"
  165. };
  166. static const char * const aud_intbus_parents[] __initconst = {
  167. "clk_null",
  168. "clk26m_ck",
  169. "mainpll_d22",
  170. "clk_null",
  171. "mainpll_d11"
  172. };
  173. static const char * const nfi2x_pad_parents[] __initconst = {
  174. "clk_null",
  175. "clk_null",
  176. "clk_null",
  177. "clk_null",
  178. "clk_null",
  179. "clk_null",
  180. "clk_null",
  181. "clk_null",
  182. "clk26m_ck",
  183. "clk_null",
  184. "clk_null",
  185. "clk_null",
  186. "clk_null",
  187. "clk_null",
  188. "clk_null",
  189. "clk_null",
  190. "clk_null",
  191. "mainpll_d12",
  192. "mainpll_d8",
  193. "clk_null",
  194. "mainpll_d6",
  195. "clk_null",
  196. "clk_null",
  197. "clk_null",
  198. "clk_null",
  199. "clk_null",
  200. "clk_null",
  201. "clk_null",
  202. "clk_null",
  203. "clk_null",
  204. "clk_null",
  205. "clk_null",
  206. "mainpll_d4",
  207. "clk_null",
  208. "clk_null",
  209. "clk_null",
  210. "clk_null",
  211. "clk_null",
  212. "clk_null",
  213. "clk_null",
  214. "clk_null",
  215. "clk_null",
  216. "clk_null",
  217. "clk_null",
  218. "clk_null",
  219. "clk_null",
  220. "clk_null",
  221. "clk_null",
  222. "clk_null",
  223. "clk_null",
  224. "clk_null",
  225. "clk_null",
  226. "clk_null",
  227. "clk_null",
  228. "clk_null",
  229. "clk_null",
  230. "clk_null",
  231. "clk_null",
  232. "clk_null",
  233. "clk_null",
  234. "clk_null",
  235. "clk_null",
  236. "clk_null",
  237. "clk_null",
  238. "clk_null",
  239. "clk_null",
  240. "clk_null",
  241. "clk_null",
  242. "clk_null",
  243. "clk_null",
  244. "clk_null",
  245. "clk_null",
  246. "clk_null",
  247. "clk_null",
  248. "clk_null",
  249. "clk_null",
  250. "clk_null",
  251. "clk_null",
  252. "clk_null",
  253. "clk_null",
  254. "clk_null",
  255. "mainpll_d10",
  256. "mainpll_d7",
  257. "clk_null",
  258. "mainpll_d5"
  259. };
  260. static const char * const nfi1x_pad_parents[] __initconst = {
  261. "ahb_infra_sel",
  262. "nfi1x_ck"
  263. };
  264. static const char * const mfg_mm_parents[] __initconst = {
  265. "clk_null",
  266. "clk_null",
  267. "clk_null",
  268. "clk_null",
  269. "clk_null",
  270. "clk_null",
  271. "clk_null",
  272. "clk_null",
  273. "csw_mux_mfg_sel",
  274. "clk_null",
  275. "clk_null",
  276. "clk_null",
  277. "clk_null",
  278. "clk_null",
  279. "clk_null",
  280. "clk_null",
  281. "mainpll_d3",
  282. "clk_null",
  283. "clk_null",
  284. "clk_null",
  285. "clk_null",
  286. "clk_null",
  287. "clk_null",
  288. "clk_null",
  289. "clk_null",
  290. "clk_null",
  291. "clk_null",
  292. "clk_null",
  293. "clk_null",
  294. "clk_null",
  295. "clk_null",
  296. "clk_null",
  297. "clk_null",
  298. "mainpll_d5",
  299. "mainpll_d7",
  300. "clk_null",
  301. "mainpll_d14"
  302. };
  303. static const char * const ddrphycfg_parents[] __initconst = {
  304. "clk26m_ck",
  305. "mainpll_d16"
  306. };
  307. static const char * const smi_mm_parents[] __initconst = {
  308. "clk26m_ck",
  309. "clk_null",
  310. "clk_null",
  311. "clk_null",
  312. "clk_null",
  313. "clk_null",
  314. "clk_null",
  315. "clk_null",
  316. "clk_null",
  317. "univpll_d4",
  318. "mainpll_d7",
  319. "clk_null",
  320. "mainpll_d14"
  321. };
  322. static const char * const usb_78m_parents[] __initconst = {
  323. "clk_null",
  324. "clk26m_ck",
  325. "univpll_d16",
  326. "clk_null",
  327. "mainpll_d20"
  328. };
  329. static const char * const scam_mm_parents[] __initconst = {
  330. "clk_null",
  331. "clk26m_ck",
  332. "mainpll_d14",
  333. "clk_null",
  334. "mainpll_d12"
  335. };
  336. static const char * const spinor_parents[] __initconst = {
  337. "clk26m_d2",
  338. "clk26m_ck",
  339. "mainpll_d40",
  340. "univpll_d24",
  341. "univpll_d20",
  342. "mainpll_d20",
  343. "mainpll_d16",
  344. "univpll_d12"
  345. };
  346. static const char * const msdc2_parents[] __initconst = {
  347. "clk26m_ck",
  348. "univpll_d6",
  349. "mainpll_d8",
  350. "univpll_d8",
  351. "mainpll_d16",
  352. "mmpll_200m",
  353. "mainpll_d12",
  354. "mmpll_d2"
  355. };
  356. static const char * const eth_parents[] __initconst = {
  357. "clk26m_ck",
  358. "mainpll_d40",
  359. "univpll_d24",
  360. "univpll_d20",
  361. "mainpll_d20"
  362. };
  363. static const char * const vdec_mm_parents[] __initconst = {
  364. "clk26m_ck",
  365. "univpll_d4",
  366. "mainpll_d4",
  367. "univpll_d5",
  368. "univpll_d6",
  369. "mainpll_d6"
  370. };
  371. static const char * const dpi0_mm_parents[] __initconst = {
  372. "clk26m_ck",
  373. "lvdspll_ck",
  374. "lvdspll_d2",
  375. "lvdspll_d4",
  376. "lvdspll_d8"
  377. };
  378. static const char * const dpi1_mm_parents[] __initconst = {
  379. "clk26m_ck",
  380. "tvdpll_d2",
  381. "tvdpll_d4",
  382. "tvdpll_d8",
  383. "tvdpll_d16"
  384. };
  385. static const char * const axi_mfg_in_parents[] __initconst = {
  386. "clk26m_ck",
  387. "mainpll_d11",
  388. "univpll_d24",
  389. "mmpll380m"
  390. };
  391. static const char * const slow_mfg_parents[] __initconst = {
  392. "clk26m_ck",
  393. "univpll_d12",
  394. "univpll_d24"
  395. };
  396. static const char * const aud1_parents[] __initconst = {
  397. "clk26m_ck",
  398. "apll1_ck"
  399. };
  400. static const char * const aud2_parents[] __initconst = {
  401. "clk26m_ck",
  402. "apll2_ck"
  403. };
  404. static const char * const aud_engen1_parents[] __initconst = {
  405. "clk26m_ck",
  406. "rg_apll1_d2_en",
  407. "rg_apll1_d4_en",
  408. "rg_apll1_d8_en"
  409. };
  410. static const char * const aud_engen2_parents[] __initconst = {
  411. "clk26m_ck",
  412. "rg_apll2_d2_en",
  413. "rg_apll2_d4_en",
  414. "rg_apll2_d8_en"
  415. };
  416. static const char * const i2c_parents[] __initconst = {
  417. "clk26m_ck",
  418. "univpll_d20",
  419. "univpll_d16",
  420. "univpll_d12"
  421. };
  422. static const char * const aud_i2s0_m_parents[] __initconst = {
  423. "rg_aud1",
  424. "rg_aud2"
  425. };
  426. static const char * const pwm_parents[] __initconst = {
  427. "clk26m_ck",
  428. "univpll_d12"
  429. };
  430. static const char * const spi_parents[] __initconst = {
  431. "clk26m_ck",
  432. "univpll_d12",
  433. "univpll_d8",
  434. "univpll_d6"
  435. };
  436. static const char * const aud_spdifin_parents[] __initconst = {
  437. "clk26m_ck",
  438. "univpll_d2"
  439. };
  440. static const char * const uart2_parents[] __initconst = {
  441. "clk26m_ck",
  442. "univpll_d24"
  443. };
  444. static const char * const bsi_parents[] __initconst = {
  445. "clk26m_ck",
  446. "mainpll_d10",
  447. "mainpll_d12",
  448. "mainpll_d20"
  449. };
  450. static const char * const dbg_atclk_parents[] __initconst = {
  451. "clk_null",
  452. "clk26m_ck",
  453. "mainpll_d5",
  454. "clk_null",
  455. "univpll_d5"
  456. };
  457. static const char * const csw_nfiecc_parents[] __initconst = {
  458. "clk_null",
  459. "mainpll_d7",
  460. "mainpll_d6",
  461. "clk_null",
  462. "mainpll_d5"
  463. };
  464. static const char * const nfiecc_parents[] __initconst = {
  465. "clk_null",
  466. "nfi2x_pad_sel",
  467. "mainpll_d4",
  468. "clk_null",
  469. "csw_nfiecc_sel"
  470. };
  471. static struct mtk_composite top_muxes[] __initdata = {
  472. /* CLK_MUX_SEL0 */
  473. MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
  474. 0x000, 0, 1),
  475. MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
  476. 0x000, 1, 1),
  477. MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
  478. 0x000, 2, 1),
  479. MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
  480. 0x000, 4, 4),
  481. MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
  482. 0x000, 8, 3),
  483. MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
  484. 0x000, 11, 3),
  485. MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
  486. 0x000, 15, 3),
  487. MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
  488. 0x000, 18, 1),
  489. MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
  490. 0x000, 19, 1),
  491. MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
  492. 0x000, 20, 3),
  493. MUX(CLK_TOP_SPM_52M_SEL, "spm_52m_sel", spm_52m_parents,
  494. 0x000, 23, 1),
  495. MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
  496. 0x000, 24, 2),
  497. MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
  498. 0x000, 26, 1),
  499. MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
  500. 0x000, 27, 3),
  501. /* CLK_MUX_SEL1 */
  502. MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
  503. 0x004, 0, 7),
  504. MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
  505. 0x004, 7, 1),
  506. MUX(CLK_TOP_MFG_MM_SEL, "mfg_mm_sel", mfg_mm_parents,
  507. 0x004, 8, 6),
  508. MUX(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
  509. 0x004, 15, 1),
  510. MUX(CLK_TOP_SMI_MM_SEL, "smi_mm_sel", smi_mm_parents,
  511. 0x004, 16, 4),
  512. MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
  513. 0x004, 20, 3),
  514. MUX(CLK_TOP_SCAM_MM_SEL, "scam_mm_sel", scam_mm_parents,
  515. 0x004, 23, 3),
  516. /* CLK_MUX_SEL8 */
  517. MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
  518. 0x040, 0, 3),
  519. MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
  520. 0x040, 3, 3),
  521. MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
  522. 0x040, 6, 3),
  523. MUX(CLK_TOP_VDEC_MM_SEL, "vdec_mm_sel", vdec_mm_parents,
  524. 0x040, 9, 3),
  525. MUX(CLK_TOP_DPI0_MM_SEL, "dpi0_mm_sel", dpi0_mm_parents,
  526. 0x040, 12, 3),
  527. MUX(CLK_TOP_DPI1_MM_SEL, "dpi1_mm_sel", dpi1_mm_parents,
  528. 0x040, 15, 3),
  529. MUX(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents,
  530. 0x040, 18, 2),
  531. MUX(CLK_TOP_SLOW_MFG_SEL, "slow_mfg_sel", slow_mfg_parents,
  532. 0x040, 20, 2),
  533. MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
  534. 0x040, 22, 1),
  535. MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
  536. 0x040, 23, 1),
  537. MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
  538. 0x040, 24, 2),
  539. MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
  540. 0x040, 26, 2),
  541. MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
  542. 0x040, 28, 2),
  543. /* CLK_SEL_9 */
  544. MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
  545. 0x044, 12, 1),
  546. MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
  547. 0x044, 13, 1),
  548. MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
  549. 0x044, 14, 1),
  550. MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
  551. 0x044, 15, 1),
  552. MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
  553. 0x044, 16, 1),
  554. MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
  555. 0x044, 17, 1),
  556. MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
  557. 0x044, 18, 1),
  558. /* CLK_MUX_SEL13 */
  559. MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
  560. 0x07c, 0, 1),
  561. MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
  562. 0x07c, 1, 2),
  563. MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
  564. 0x07c, 3, 1),
  565. MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
  566. 0x07c, 4, 1),
  567. MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
  568. 0x07c, 5, 2),
  569. MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
  570. 0x07c, 7, 3),
  571. MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
  572. 0x07c, 10, 3),
  573. MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
  574. 0x07c, 13, 3),
  575. };
  576. static const char * const ifr_mux1_parents[] __initconst = {
  577. "clk26m_ck",
  578. "armpll",
  579. "univpll",
  580. "mainpll_d2"
  581. };
  582. static const char * const ifr_eth_25m_parents[] __initconst = {
  583. "eth_d2_ck",
  584. "rg_eth"
  585. };
  586. static const char * const ifr_i2c0_parents[] __initconst = {
  587. "ahb_infra_d2",
  588. "rg_i2c"
  589. };
  590. static const struct mtk_composite ifr_muxes[] __initconst = {
  591. MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
  592. 2, 2),
  593. MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
  594. 0, 1),
  595. MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
  596. 1, 1),
  597. MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
  598. 2, 1),
  599. MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
  600. 3, 1),
  601. };
  602. #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
  603. .id = _id, \
  604. .name = _name, \
  605. .parent_name = _parent, \
  606. .div_reg = _reg, \
  607. .div_shift = _shift, \
  608. .div_width = _width, \
  609. }
  610. static const struct mtk_clk_divider top_adj_divs[] = {
  611. DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
  612. 0x0048, 0, 8),
  613. DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
  614. 0x0048, 8, 8),
  615. DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
  616. 0x0048, 16, 8),
  617. DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
  618. 0x0048, 24, 8),
  619. DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
  620. 0x004c, 0, 8),
  621. DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
  622. 0x004c, 8, 8),
  623. DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
  624. 0x004c, 16, 8),
  625. DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
  626. 0x004c, 24, 8),
  627. DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
  628. 0x0078, 0, 8),
  629. };
  630. #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \
  631. .id = _id, \
  632. .name = _name, \
  633. .parent_name = _parent, \
  634. .div_reg = _reg, \
  635. .div_shift = _shift, \
  636. .div_width = _width, \
  637. .clk_divider_flags = _flag, \
  638. }
  639. static const struct mtk_clk_divider apmixed_adj_divs[] = {
  640. DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll",
  641. 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),
  642. };
  643. static const struct mtk_gate_regs top0_cg_regs = {
  644. .set_ofs = 0x50,
  645. .clr_ofs = 0x80,
  646. .sta_ofs = 0x20,
  647. };
  648. static const struct mtk_gate_regs top1_cg_regs = {
  649. .set_ofs = 0x54,
  650. .clr_ofs = 0x84,
  651. .sta_ofs = 0x24,
  652. };
  653. static const struct mtk_gate_regs top2_cg_regs = {
  654. .set_ofs = 0x6c,
  655. .clr_ofs = 0x9c,
  656. .sta_ofs = 0x3c,
  657. };
  658. static const struct mtk_gate_regs top3_cg_regs = {
  659. .set_ofs = 0xa0,
  660. .clr_ofs = 0xb0,
  661. .sta_ofs = 0x70,
  662. };
  663. static const struct mtk_gate_regs top4_cg_regs = {
  664. .set_ofs = 0xa4,
  665. .clr_ofs = 0xb4,
  666. .sta_ofs = 0x74,
  667. };
  668. static const struct mtk_gate_regs top5_cg_regs = {
  669. .set_ofs = 0x44,
  670. .clr_ofs = 0x44,
  671. .sta_ofs = 0x44,
  672. };
  673. #define GATE_TOP0(_id, _name, _parent, _shift) { \
  674. .id = _id, \
  675. .name = _name, \
  676. .parent_name = _parent, \
  677. .regs = &top0_cg_regs, \
  678. .shift = _shift, \
  679. .ops = &mtk_clk_gate_ops_setclr, \
  680. }
  681. #define GATE_TOP0_I(_id, _name, _parent, _shift) { \
  682. .id = _id, \
  683. .name = _name, \
  684. .parent_name = _parent, \
  685. .regs = &top0_cg_regs, \
  686. .shift = _shift, \
  687. .ops = &mtk_clk_gate_ops_setclr_inv, \
  688. }
  689. #define GATE_TOP1(_id, _name, _parent, _shift) { \
  690. .id = _id, \
  691. .name = _name, \
  692. .parent_name = _parent, \
  693. .regs = &top1_cg_regs, \
  694. .shift = _shift, \
  695. .ops = &mtk_clk_gate_ops_setclr, \
  696. }
  697. #define GATE_TOP2(_id, _name, _parent, _shift) { \
  698. .id = _id, \
  699. .name = _name, \
  700. .parent_name = _parent, \
  701. .regs = &top2_cg_regs, \
  702. .shift = _shift, \
  703. .ops = &mtk_clk_gate_ops_setclr, \
  704. }
  705. #define GATE_TOP2_I(_id, _name, _parent, _shift) { \
  706. .id = _id, \
  707. .name = _name, \
  708. .parent_name = _parent, \
  709. .regs = &top2_cg_regs, \
  710. .shift = _shift, \
  711. .ops = &mtk_clk_gate_ops_setclr_inv, \
  712. }
  713. #define GATE_TOP3(_id, _name, _parent, _shift) { \
  714. .id = _id, \
  715. .name = _name, \
  716. .parent_name = _parent, \
  717. .regs = &top3_cg_regs, \
  718. .shift = _shift, \
  719. .ops = &mtk_clk_gate_ops_setclr, \
  720. }
  721. #define GATE_TOP4_I(_id, _name, _parent, _shift) { \
  722. .id = _id, \
  723. .name = _name, \
  724. .parent_name = _parent, \
  725. .regs = &top4_cg_regs, \
  726. .shift = _shift, \
  727. .ops = &mtk_clk_gate_ops_setclr_inv, \
  728. }
  729. #define GATE_TOP5(_id, _name, _parent, _shift) { \
  730. .id = _id, \
  731. .name = _name, \
  732. .parent_name = _parent, \
  733. .regs = &top5_cg_regs, \
  734. .shift = _shift, \
  735. .ops = &mtk_clk_gate_ops_no_setclr, \
  736. }
  737. static const struct mtk_gate top_clks[] __initconst = {
  738. /* TOP0 */
  739. GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
  740. GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1),
  741. GATE_TOP0(CLK_TOP_MFG_MM, "mfg_mm", "mfg_mm_sel", 2),
  742. GATE_TOP0(CLK_TOP_SPM_52M, "spm_52m", "spm_52m_sel", 3),
  743. GATE_TOP0_I(CLK_TOP_MIPI_26M_DBG, "mipi_26m_dbg", "mipi_26m", 4),
  744. GATE_TOP0(CLK_TOP_SCAM_MM, "scam_mm", "scam_mm_sel", 5),
  745. GATE_TOP0(CLK_TOP_SMI_MM, "smi_mm", "smi_mm_sel", 9),
  746. /* TOP1 */
  747. GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
  748. GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
  749. GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
  750. GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
  751. GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
  752. GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
  753. GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
  754. GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
  755. GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
  756. GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
  757. GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
  758. GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
  759. GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
  760. GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
  761. GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
  762. GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
  763. GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
  764. GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
  765. GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
  766. GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
  767. GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
  768. GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
  769. GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
  770. GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
  771. GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
  772. GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
  773. GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
  774. GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
  775. GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
  776. GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
  777. /* TOP2 */
  778. GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
  779. GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
  780. GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
  781. GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
  782. GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
  783. GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
  784. GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
  785. GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
  786. GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
  787. GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
  788. GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
  789. GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
  790. GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
  791. GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
  792. GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
  793. 15),
  794. GATE_TOP2(CLK_TOP_26M_HDMI_SIFM, "hdmi_sifm_26m", "clk26m_ck", 16),
  795. GATE_TOP2(CLK_TOP_26M_CEC, "cec_26m", "clk26m_ck", 17),
  796. GATE_TOP2(CLK_TOP_32K_CEC, "cec_32k", "clk32k", 18),
  797. GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
  798. GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
  799. GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
  800. GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
  801. GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
  802. GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
  803. GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
  804. GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
  805. GATE_TOP2(CLK_TOP_GCPU_B, "gcpu_b", "ahb_infra_sel", 27),
  806. GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
  807. GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
  808. GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
  809. GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
  810. /* TOP3 */
  811. GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
  812. GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
  813. GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
  814. GATE_TOP3(CLK_TOP_RG_VDEC, "rg_vdec", "vdec_mm_sel", 3),
  815. GATE_TOP3(CLK_TOP_RG_FDPI0, "rg_fdpi0", "dpi0_mm_sel", 4),
  816. GATE_TOP3(CLK_TOP_RG_FDPI1, "rg_fdpi1", "dpi1_mm_sel", 5),
  817. GATE_TOP3(CLK_TOP_RG_AXI_MFG, "rg_axi_mfg", "axi_mfg_in_sel", 6),
  818. GATE_TOP3(CLK_TOP_RG_SLOW_MFG, "rg_slow_mfg", "slow_mfg_sel", 7),
  819. GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
  820. GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
  821. GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
  822. GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
  823. GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
  824. GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
  825. GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
  826. 14),
  827. GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
  828. GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
  829. GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
  830. GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
  831. /* TOP4 */
  832. GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
  833. GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
  834. GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
  835. GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
  836. GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
  837. GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
  838. /* TOP5 */
  839. GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
  840. GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
  841. GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
  842. GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
  843. GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
  844. GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
  845. GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
  846. GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
  847. GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
  848. };
  849. static void __init mtk_topckgen_init(struct device_node *node)
  850. {
  851. struct clk_onecell_data *clk_data;
  852. int r;
  853. void __iomem *base;
  854. base = of_iomap(node, 0);
  855. if (!base) {
  856. pr_err("%s(): ioremap failed\n", __func__);
  857. return;
  858. }
  859. clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK);
  860. mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
  861. clk_data);
  862. mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
  863. mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
  864. mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
  865. &mt8167_clk_lock, clk_data);
  866. mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
  867. base, &mt8167_clk_lock, clk_data);
  868. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  869. if (r)
  870. pr_err("%s(): could not register clock provider: %d\n",
  871. __func__, r);
  872. }
  873. CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init);
  874. static void __init mtk_infracfg_init(struct device_node *node)
  875. {
  876. struct clk_onecell_data *clk_data;
  877. int r;
  878. void __iomem *base;
  879. base = of_iomap(node, 0);
  880. if (!base) {
  881. pr_err("%s(): ioremap failed\n", __func__);
  882. return;
  883. }
  884. clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
  885. mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
  886. &mt8167_clk_lock, clk_data);
  887. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  888. if (r)
  889. pr_err("%s(): could not register clock provider: %d\n",
  890. __func__, r);
  891. }
  892. CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init);
  893. #define MT8167_PLL_FMAX (2500UL * MHZ)
  894. #define CON0_MT8167_RST_BAR BIT(27)
  895. #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  896. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
  897. _pcw_shift, _div_table) { \
  898. .id = _id, \
  899. .name = _name, \
  900. .reg = _reg, \
  901. .pwr_reg = _pwr_reg, \
  902. .en_mask = _en_mask, \
  903. .flags = _flags, \
  904. .rst_bar_mask = CON0_MT8167_RST_BAR, \
  905. .fmax = MT8167_PLL_FMAX, \
  906. .pcwbits = _pcwbits, \
  907. .pd_reg = _pd_reg, \
  908. .pd_shift = _pd_shift, \
  909. .tuner_reg = _tuner_reg, \
  910. .pcw_reg = _pcw_reg, \
  911. .pcw_shift = _pcw_shift, \
  912. .div_table = _div_table, \
  913. }
  914. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  915. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
  916. _pcw_shift) \
  917. PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  918. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
  919. NULL)
  920. static const struct mtk_pll_div_table mmpll_div_table[] = {
  921. { .div = 0, .freq = MT8167_PLL_FMAX },
  922. { .div = 1, .freq = 1000000000 },
  923. { .div = 2, .freq = 604500000 },
  924. { .div = 3, .freq = 253500000 },
  925. { .div = 4, .freq = 126750000 },
  926. { } /* sentinel */
  927. };
  928. static const struct mtk_pll_data plls[] = {
  929. PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
  930. 21, 0x0104, 24, 0, 0x0104, 0),
  931. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
  932. HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
  933. PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
  934. HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
  935. PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
  936. 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
  937. PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
  938. 31, 0x0180, 1, 0x0194, 0x0184, 0),
  939. PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
  940. 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
  941. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0x00000001, 0,
  942. 21, 0x01C4, 24, 0, 0x01C4, 0),
  943. PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0x00000001, 0,
  944. 21, 0x01E4, 24, 0, 0x01E4, 0),
  945. };
  946. static void __init mtk_apmixedsys_init(struct device_node *node)
  947. {
  948. struct clk_onecell_data *clk_data;
  949. void __iomem *base;
  950. int r;
  951. base = of_iomap(node, 0);
  952. if (!base) {
  953. pr_err("%s(): ioremap failed\n", __func__);
  954. return;
  955. }
  956. clk_data = mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK);
  957. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  958. mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs),
  959. base, &mt8167_clk_lock, clk_data);
  960. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  961. if (r)
  962. pr_err("%s(): could not register clock provider: %d\n",
  963. __func__, r);
  964. }
  965. CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys",
  966. mtk_apmixedsys_init);