clk-mt8167-aud.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2020 MediaTek Inc.
  4. * Copyright (c) 2020 BayLibre, SAS
  5. * Author: James Liao <jamesjj.liao@mediatek.com>
  6. * Fabien Parent <fparent@baylibre.com>
  7. */
  8. #include <linux/clk-provider.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include "clk-mtk.h"
  14. #include "clk-gate.h"
  15. #include <dt-bindings/clock/mt8167-clk.h>
  16. static const struct mtk_gate_regs aud_cg_regs = {
  17. .set_ofs = 0x0,
  18. .clr_ofs = 0x0,
  19. .sta_ofs = 0x0,
  20. };
  21. #define GATE_AUD(_id, _name, _parent, _shift) { \
  22. .id = _id, \
  23. .name = _name, \
  24. .parent_name = _parent, \
  25. .regs = &aud_cg_regs, \
  26. .shift = _shift, \
  27. .ops = &mtk_clk_gate_ops_no_setclr, \
  28. }
  29. static const struct mtk_gate aud_clks[] __initconst = {
  30. GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2),
  31. GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6),
  32. GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8),
  33. GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9),
  34. GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15),
  35. GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18),
  36. GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19),
  37. GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20),
  38. GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21),
  39. GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24),
  40. GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25),
  41. GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26),
  42. GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27),
  43. };
  44. static void __init mtk_audsys_init(struct device_node *node)
  45. {
  46. struct clk_onecell_data *clk_data;
  47. int r;
  48. clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
  49. mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
  50. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  51. if (r)
  52. pr_err("%s(): could not register clock provider: %d\n",
  53. __func__, r);
  54. }
  55. CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init);