clk-mt7622.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Chen Zhong <chen.zhong@mediatek.com>
  5. * Sean Wang <sean.wang@mediatek.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include "clk-mtk.h"
  13. #include "clk-gate.h"
  14. #include "clk-cpumux.h"
  15. #include <dt-bindings/clock/mt7622-clk.h>
  16. #include <linux/clk.h> /* for consumer */
  17. #define MT7622_PLL_FMAX (2500UL * MHZ)
  18. #define CON0_MT7622_RST_BAR BIT(27)
  19. #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
  20. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
  21. _pcw_shift, _div_table, _parent_name) { \
  22. .id = _id, \
  23. .name = _name, \
  24. .reg = _reg, \
  25. .pwr_reg = _pwr_reg, \
  26. .en_mask = _en_mask, \
  27. .flags = _flags, \
  28. .rst_bar_mask = CON0_MT7622_RST_BAR, \
  29. .fmax = MT7622_PLL_FMAX, \
  30. .pcwbits = _pcwbits, \
  31. .pd_reg = _pd_reg, \
  32. .pd_shift = _pd_shift, \
  33. .tuner_reg = _tuner_reg, \
  34. .pcw_reg = _pcw_reg, \
  35. .pcw_shift = _pcw_shift, \
  36. .div_table = _div_table, \
  37. .parent_name = _parent_name, \
  38. }
  39. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  40. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
  41. _pcw_shift) \
  42. PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
  43. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
  44. NULL, "clkxtal")
  45. #define GATE_APMIXED(_id, _name, _parent, _shift) { \
  46. .id = _id, \
  47. .name = _name, \
  48. .parent_name = _parent, \
  49. .regs = &apmixed_cg_regs, \
  50. .shift = _shift, \
  51. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  52. }
  53. #define GATE_INFRA(_id, _name, _parent, _shift) { \
  54. .id = _id, \
  55. .name = _name, \
  56. .parent_name = _parent, \
  57. .regs = &infra_cg_regs, \
  58. .shift = _shift, \
  59. .ops = &mtk_clk_gate_ops_setclr, \
  60. }
  61. #define GATE_TOP0(_id, _name, _parent, _shift) { \
  62. .id = _id, \
  63. .name = _name, \
  64. .parent_name = _parent, \
  65. .regs = &top0_cg_regs, \
  66. .shift = _shift, \
  67. .ops = &mtk_clk_gate_ops_no_setclr, \
  68. }
  69. #define GATE_TOP1(_id, _name, _parent, _shift) { \
  70. .id = _id, \
  71. .name = _name, \
  72. .parent_name = _parent, \
  73. .regs = &top1_cg_regs, \
  74. .shift = _shift, \
  75. .ops = &mtk_clk_gate_ops_no_setclr, \
  76. }
  77. #define GATE_PERI0(_id, _name, _parent, _shift) { \
  78. .id = _id, \
  79. .name = _name, \
  80. .parent_name = _parent, \
  81. .regs = &peri0_cg_regs, \
  82. .shift = _shift, \
  83. .ops = &mtk_clk_gate_ops_setclr, \
  84. }
  85. #define GATE_PERI1(_id, _name, _parent, _shift) { \
  86. .id = _id, \
  87. .name = _name, \
  88. .parent_name = _parent, \
  89. .regs = &peri1_cg_regs, \
  90. .shift = _shift, \
  91. .ops = &mtk_clk_gate_ops_setclr, \
  92. }
  93. static DEFINE_SPINLOCK(mt7622_clk_lock);
  94. static const char * const infra_mux1_parents[] = {
  95. "clkxtal",
  96. "armpll",
  97. "main_core_en",
  98. "armpll"
  99. };
  100. static const char * const axi_parents[] = {
  101. "clkxtal",
  102. "syspll1_d2",
  103. "syspll_d5",
  104. "syspll1_d4",
  105. "univpll_d5",
  106. "univpll2_d2",
  107. "univpll_d7"
  108. };
  109. static const char * const mem_parents[] = {
  110. "clkxtal",
  111. "dmpll_ck"
  112. };
  113. static const char * const ddrphycfg_parents[] = {
  114. "clkxtal",
  115. "syspll1_d8"
  116. };
  117. static const char * const eth_parents[] = {
  118. "clkxtal",
  119. "syspll1_d2",
  120. "univpll1_d2",
  121. "syspll1_d4",
  122. "univpll_d5",
  123. "clk_null",
  124. "univpll_d7"
  125. };
  126. static const char * const pwm_parents[] = {
  127. "clkxtal",
  128. "univpll2_d4"
  129. };
  130. static const char * const f10m_ref_parents[] = {
  131. "clkxtal",
  132. "syspll4_d16"
  133. };
  134. static const char * const nfi_infra_parents[] = {
  135. "clkxtal",
  136. "clkxtal",
  137. "clkxtal",
  138. "clkxtal",
  139. "clkxtal",
  140. "clkxtal",
  141. "clkxtal",
  142. "clkxtal",
  143. "univpll2_d8",
  144. "syspll1_d8",
  145. "univpll1_d8",
  146. "syspll4_d2",
  147. "univpll2_d4",
  148. "univpll3_d2",
  149. "syspll1_d4"
  150. };
  151. static const char * const flash_parents[] = {
  152. "clkxtal",
  153. "univpll_d80_d4",
  154. "syspll2_d8",
  155. "syspll3_d4",
  156. "univpll3_d4",
  157. "univpll1_d8",
  158. "syspll2_d4",
  159. "univpll2_d4"
  160. };
  161. static const char * const uart_parents[] = {
  162. "clkxtal",
  163. "univpll2_d8"
  164. };
  165. static const char * const spi0_parents[] = {
  166. "clkxtal",
  167. "syspll3_d2",
  168. "clkxtal",
  169. "syspll2_d4",
  170. "syspll4_d2",
  171. "univpll2_d4",
  172. "univpll1_d8",
  173. "clkxtal"
  174. };
  175. static const char * const spi1_parents[] = {
  176. "clkxtal",
  177. "syspll3_d2",
  178. "clkxtal",
  179. "syspll4_d4",
  180. "syspll4_d2",
  181. "univpll2_d4",
  182. "univpll1_d8",
  183. "clkxtal"
  184. };
  185. static const char * const msdc30_0_parents[] = {
  186. "clkxtal",
  187. "univpll2_d16",
  188. "univ48m"
  189. };
  190. static const char * const a1sys_hp_parents[] = {
  191. "clkxtal",
  192. "aud1pll_ck",
  193. "aud2pll_ck",
  194. "clkxtal"
  195. };
  196. static const char * const intdir_parents[] = {
  197. "clkxtal",
  198. "syspll_d2",
  199. "univpll_d2",
  200. "sgmiipll_ck"
  201. };
  202. static const char * const aud_intbus_parents[] = {
  203. "clkxtal",
  204. "syspll1_d4",
  205. "syspll4_d2",
  206. "syspll3_d2"
  207. };
  208. static const char * const pmicspi_parents[] = {
  209. "clkxtal",
  210. "clk_null",
  211. "clk_null",
  212. "clk_null",
  213. "clk_null",
  214. "univpll2_d16"
  215. };
  216. static const char * const atb_parents[] = {
  217. "clkxtal",
  218. "syspll1_d2",
  219. "syspll_d5"
  220. };
  221. static const char * const audio_parents[] = {
  222. "clkxtal",
  223. "syspll3_d4",
  224. "syspll4_d4",
  225. "univpll1_d16"
  226. };
  227. static const char * const usb20_parents[] = {
  228. "clkxtal",
  229. "univpll3_d4",
  230. "syspll1_d8",
  231. "clkxtal"
  232. };
  233. static const char * const aud1_parents[] = {
  234. "clkxtal",
  235. "aud1pll_ck"
  236. };
  237. static const char * const aud2_parents[] = {
  238. "clkxtal",
  239. "aud2pll_ck"
  240. };
  241. static const char * const asm_l_parents[] = {
  242. "clkxtal",
  243. "syspll_d5",
  244. "univpll2_d2",
  245. "univpll2_d4"
  246. };
  247. static const char * const apll1_ck_parents[] = {
  248. "aud1_sel",
  249. "aud2_sel"
  250. };
  251. static const char * const peribus_ck_parents[] = {
  252. "syspll1_d8",
  253. "syspll1_d4"
  254. };
  255. static const struct mtk_gate_regs apmixed_cg_regs = {
  256. .set_ofs = 0x8,
  257. .clr_ofs = 0x8,
  258. .sta_ofs = 0x8,
  259. };
  260. static const struct mtk_gate_regs infra_cg_regs = {
  261. .set_ofs = 0x40,
  262. .clr_ofs = 0x44,
  263. .sta_ofs = 0x48,
  264. };
  265. static const struct mtk_gate_regs top0_cg_regs = {
  266. .set_ofs = 0x120,
  267. .clr_ofs = 0x120,
  268. .sta_ofs = 0x120,
  269. };
  270. static const struct mtk_gate_regs top1_cg_regs = {
  271. .set_ofs = 0x128,
  272. .clr_ofs = 0x128,
  273. .sta_ofs = 0x128,
  274. };
  275. static const struct mtk_gate_regs peri0_cg_regs = {
  276. .set_ofs = 0x8,
  277. .clr_ofs = 0x10,
  278. .sta_ofs = 0x18,
  279. };
  280. static const struct mtk_gate_regs peri1_cg_regs = {
  281. .set_ofs = 0xC,
  282. .clr_ofs = 0x14,
  283. .sta_ofs = 0x1C,
  284. };
  285. static const struct mtk_pll_data plls[] = {
  286. PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
  287. PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
  288. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
  289. HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
  290. PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
  291. HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
  292. PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
  293. 0, 21, 0x0300, 1, 0, 0x0304, 0),
  294. PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
  295. 0, 21, 0x0314, 1, 0, 0x0318, 0),
  296. PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
  297. 0, 31, 0x0324, 1, 0, 0x0328, 0),
  298. PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
  299. 0, 31, 0x0334, 1, 0, 0x0338, 0),
  300. PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
  301. 0, 21, 0x0344, 1, 0, 0x0348, 0),
  302. PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
  303. 0, 21, 0x0358, 1, 0, 0x035C, 0),
  304. };
  305. static const struct mtk_gate apmixed_clks[] = {
  306. GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
  307. };
  308. static const struct mtk_gate infra_clks[] = {
  309. GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
  310. GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
  311. GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
  312. GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
  313. GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
  314. GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
  315. };
  316. static const struct mtk_fixed_clk top_fixed_clks[] = {
  317. FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
  318. 31250000),
  319. FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
  320. 31250000),
  321. FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
  322. 125000000),
  323. FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
  324. 125000000),
  325. FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
  326. 250000000),
  327. FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
  328. 250000000),
  329. FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
  330. 33333333),
  331. FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
  332. 50000000),
  333. FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
  334. 50000000),
  335. FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
  336. 50000000),
  337. };
  338. static const struct mtk_fixed_factor top_divs[] = {
  339. FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
  340. FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
  341. FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
  342. FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
  343. FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
  344. FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
  345. FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
  346. FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
  347. FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  348. FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
  349. FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
  350. FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
  351. FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
  352. FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
  353. FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  354. FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
  355. FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
  356. FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
  357. FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
  358. FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
  359. FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
  360. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  361. FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
  362. FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
  363. FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
  364. FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
  365. FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
  366. FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
  367. FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
  368. FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
  369. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  370. FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
  371. FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
  372. FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
  373. FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  374. FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
  375. FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
  376. FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
  377. FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
  378. FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
  379. FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
  380. FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
  381. FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
  382. FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
  383. FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
  384. FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
  385. };
  386. static const struct mtk_gate top_clks[] = {
  387. /* TOP0 */
  388. GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
  389. GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
  390. GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
  391. 2),
  392. GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
  393. 3),
  394. GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
  395. 4),
  396. GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
  397. 5),
  398. /* TOP1 */
  399. GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
  400. GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
  401. };
  402. static const struct mtk_clk_divider top_adj_divs[] = {
  403. DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
  404. 0x120, 24, 3),
  405. DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
  406. 0x120, 28, 3),
  407. DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
  408. 0x124, 0, 7),
  409. DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
  410. 0x124, 8, 7),
  411. DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
  412. 0x124, 16, 7),
  413. DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
  414. 0x124, 24, 7),
  415. DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
  416. 0x128, 8, 7),
  417. DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
  418. 0x128, 24, 7),
  419. };
  420. static const struct mtk_gate peri_clks[] = {
  421. /* PERI0 */
  422. GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
  423. GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
  424. GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
  425. GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
  426. GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
  427. GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
  428. GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
  429. GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
  430. GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
  431. GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
  432. GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
  433. GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
  434. GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
  435. GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
  436. GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
  437. GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
  438. GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
  439. GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
  440. GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
  441. GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
  442. GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
  443. GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
  444. GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
  445. GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
  446. GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
  447. GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
  448. GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
  449. /* PERI1 */
  450. GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
  451. GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
  452. };
  453. static struct mtk_composite infra_muxes[] = {
  454. MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
  455. 0x000, 2, 2),
  456. };
  457. static struct mtk_composite top_muxes[] = {
  458. /* CLK_CFG_0 */
  459. MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
  460. 0x040, 0, 3, 7),
  461. MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
  462. 0x040, 8, 1, 15),
  463. MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
  464. 0x040, 16, 1, 23),
  465. MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
  466. 0x040, 24, 3, 31),
  467. /* CLK_CFG_1 */
  468. MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
  469. 0x050, 0, 2, 7),
  470. MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
  471. 0x050, 8, 1, 15),
  472. MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
  473. 0x050, 16, 4, 23),
  474. MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
  475. 0x050, 24, 3, 31),
  476. /* CLK_CFG_2 */
  477. MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
  478. 0x060, 0, 1, 7),
  479. MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
  480. 0x060, 8, 3, 15),
  481. MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
  482. 0x060, 16, 3, 23),
  483. MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
  484. 0x060, 24, 3, 31),
  485. /* CLK_CFG_3 */
  486. MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
  487. 0x070, 0, 3, 7),
  488. MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
  489. 0x070, 8, 3, 15),
  490. MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
  491. 0x070, 16, 2, 23),
  492. MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
  493. 0x070, 24, 2, 31),
  494. /* CLK_CFG_4 */
  495. MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
  496. 0x080, 0, 2, 7),
  497. MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
  498. 0x080, 8, 2, 15),
  499. MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
  500. 0x080, 16, 3, 23),
  501. MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
  502. 0x080, 24, 2, 31),
  503. /* CLK_CFG_5 */
  504. MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
  505. 0x090, 0, 2, 7),
  506. MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
  507. 0x090, 8, 3, 15),
  508. MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
  509. 0x090, 16, 2, 23),
  510. MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
  511. 0x090, 24, 2, 31),
  512. /* CLK_CFG_6 */
  513. MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
  514. 0x0A0, 0, 1, 7),
  515. MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
  516. 0x0A0, 8, 1, 15),
  517. MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
  518. 0x0A0, 16, 1, 23),
  519. MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
  520. 0x0A0, 24, 1, 31),
  521. /* CLK_CFG_7 */
  522. MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
  523. 0x0B0, 0, 2, 7),
  524. MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
  525. 0x0B0, 8, 2, 15),
  526. MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
  527. 0x0B0, 16, 2, 23),
  528. /* CLK_AUDDIV_0 */
  529. MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
  530. 0x120, 6, 1),
  531. MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
  532. 0x120, 7, 1),
  533. MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
  534. 0x120, 8, 1),
  535. MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
  536. 0x120, 9, 1),
  537. MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
  538. 0x120, 10, 1),
  539. MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
  540. 0x120, 11, 1),
  541. };
  542. static struct mtk_composite peri_muxes[] = {
  543. /* PERI_GLOBALCON_CKSEL */
  544. MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
  545. };
  546. static int mtk_topckgen_init(struct platform_device *pdev)
  547. {
  548. struct clk_onecell_data *clk_data;
  549. void __iomem *base;
  550. struct device_node *node = pdev->dev.of_node;
  551. base = devm_platform_ioremap_resource(pdev, 0);
  552. if (IS_ERR(base))
  553. return PTR_ERR(base);
  554. clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
  555. mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  556. clk_data);
  557. mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
  558. clk_data);
  559. mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
  560. base, &mt7622_clk_lock, clk_data);
  561. mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
  562. base, &mt7622_clk_lock, clk_data);
  563. mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  564. clk_data);
  565. clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
  566. clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
  567. clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
  568. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  569. }
  570. static int mtk_infrasys_init(struct platform_device *pdev)
  571. {
  572. struct device_node *node = pdev->dev.of_node;
  573. struct clk_onecell_data *clk_data;
  574. int r;
  575. clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  576. mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  577. clk_data);
  578. mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
  579. clk_data);
  580. r = of_clk_add_provider(node, of_clk_src_onecell_get,
  581. clk_data);
  582. if (r)
  583. return r;
  584. mtk_register_reset_controller(node, 1, 0x30);
  585. return 0;
  586. }
  587. static int mtk_apmixedsys_init(struct platform_device *pdev)
  588. {
  589. struct clk_onecell_data *clk_data;
  590. struct device_node *node = pdev->dev.of_node;
  591. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
  592. if (!clk_data)
  593. return -ENOMEM;
  594. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
  595. clk_data);
  596. mtk_clk_register_gates(node, apmixed_clks,
  597. ARRAY_SIZE(apmixed_clks), clk_data);
  598. clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
  599. clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
  600. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  601. }
  602. static int mtk_pericfg_init(struct platform_device *pdev)
  603. {
  604. struct clk_onecell_data *clk_data;
  605. void __iomem *base;
  606. int r;
  607. struct device_node *node = pdev->dev.of_node;
  608. base = devm_platform_ioremap_resource(pdev, 0);
  609. if (IS_ERR(base))
  610. return PTR_ERR(base);
  611. clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
  612. mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  613. clk_data);
  614. mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
  615. &mt7622_clk_lock, clk_data);
  616. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  617. if (r)
  618. return r;
  619. clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
  620. mtk_register_reset_controller(node, 2, 0x0);
  621. return 0;
  622. }
  623. static const struct of_device_id of_match_clk_mt7622[] = {
  624. {
  625. .compatible = "mediatek,mt7622-apmixedsys",
  626. .data = mtk_apmixedsys_init,
  627. }, {
  628. .compatible = "mediatek,mt7622-infracfg",
  629. .data = mtk_infrasys_init,
  630. }, {
  631. .compatible = "mediatek,mt7622-topckgen",
  632. .data = mtk_topckgen_init,
  633. }, {
  634. .compatible = "mediatek,mt7622-pericfg",
  635. .data = mtk_pericfg_init,
  636. }, {
  637. /* sentinel */
  638. }
  639. };
  640. static int clk_mt7622_probe(struct platform_device *pdev)
  641. {
  642. int (*clk_init)(struct platform_device *);
  643. int r;
  644. clk_init = of_device_get_match_data(&pdev->dev);
  645. if (!clk_init)
  646. return -EINVAL;
  647. r = clk_init(pdev);
  648. if (r)
  649. dev_err(&pdev->dev,
  650. "could not register clock provider: %s: %d\n",
  651. pdev->name, r);
  652. return r;
  653. }
  654. static struct platform_driver clk_mt7622_drv = {
  655. .probe = clk_mt7622_probe,
  656. .driver = {
  657. .name = "clk-mt7622",
  658. .of_match_table = of_match_clk_mt7622,
  659. },
  660. };
  661. static int clk_mt7622_init(void)
  662. {
  663. return platform_driver_register(&clk_mt7622_drv);
  664. }
  665. arch_initcall(clk_mt7622_init);