clk-mt7622-hif.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Chen Zhong <chen.zhong@mediatek.com>
  5. * Sean Wang <sean.wang@mediatek.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include "clk-mtk.h"
  13. #include "clk-gate.h"
  14. #include <dt-bindings/clock/mt7622-clk.h>
  15. #define GATE_PCIE(_id, _name, _parent, _shift) { \
  16. .id = _id, \
  17. .name = _name, \
  18. .parent_name = _parent, \
  19. .regs = &pcie_cg_regs, \
  20. .shift = _shift, \
  21. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  22. }
  23. #define GATE_SSUSB(_id, _name, _parent, _shift) { \
  24. .id = _id, \
  25. .name = _name, \
  26. .parent_name = _parent, \
  27. .regs = &ssusb_cg_regs, \
  28. .shift = _shift, \
  29. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  30. }
  31. static const struct mtk_gate_regs pcie_cg_regs = {
  32. .set_ofs = 0x30,
  33. .clr_ofs = 0x30,
  34. .sta_ofs = 0x30,
  35. };
  36. static const struct mtk_gate_regs ssusb_cg_regs = {
  37. .set_ofs = 0x30,
  38. .clr_ofs = 0x30,
  39. .sta_ofs = 0x30,
  40. };
  41. static const struct mtk_gate ssusb_clks[] = {
  42. GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
  43. "to_u2_phy_1p", 0),
  44. GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
  45. GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
  46. GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
  47. GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
  48. GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
  49. };
  50. static const struct mtk_gate pcie_clks[] = {
  51. GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
  52. GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
  53. GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
  54. GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
  55. GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
  56. GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
  57. GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
  58. GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
  59. GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
  60. GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
  61. GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
  62. GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
  63. GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
  64. GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
  65. GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
  66. GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
  67. GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
  68. };
  69. static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
  70. {
  71. struct clk_onecell_data *clk_data;
  72. struct device_node *node = pdev->dev.of_node;
  73. int r;
  74. clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
  75. mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
  76. clk_data);
  77. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  78. if (r)
  79. dev_err(&pdev->dev,
  80. "could not register clock provider: %s: %d\n",
  81. pdev->name, r);
  82. mtk_register_reset_controller(node, 1, 0x34);
  83. return r;
  84. }
  85. static int clk_mt7622_pciesys_init(struct platform_device *pdev)
  86. {
  87. struct clk_onecell_data *clk_data;
  88. struct device_node *node = pdev->dev.of_node;
  89. int r;
  90. clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
  91. mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
  92. clk_data);
  93. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  94. if (r)
  95. dev_err(&pdev->dev,
  96. "could not register clock provider: %s: %d\n",
  97. pdev->name, r);
  98. mtk_register_reset_controller(node, 1, 0x34);
  99. return r;
  100. }
  101. static const struct of_device_id of_match_clk_mt7622_hif[] = {
  102. {
  103. .compatible = "mediatek,mt7622-pciesys",
  104. .data = clk_mt7622_pciesys_init,
  105. }, {
  106. .compatible = "mediatek,mt7622-ssusbsys",
  107. .data = clk_mt7622_ssusbsys_init,
  108. }, {
  109. /* sentinel */
  110. }
  111. };
  112. static int clk_mt7622_hif_probe(struct platform_device *pdev)
  113. {
  114. int (*clk_init)(struct platform_device *);
  115. int r;
  116. clk_init = of_device_get_match_data(&pdev->dev);
  117. if (!clk_init)
  118. return -EINVAL;
  119. r = clk_init(pdev);
  120. if (r)
  121. dev_err(&pdev->dev,
  122. "could not register clock provider: %s: %d\n",
  123. pdev->name, r);
  124. return r;
  125. }
  126. static struct platform_driver clk_mt7622_hif_drv = {
  127. .probe = clk_mt7622_hif_probe,
  128. .driver = {
  129. .name = "clk-mt7622-hif",
  130. .of_match_table = of_match_clk_mt7622_hif,
  131. },
  132. };
  133. builtin_platform_driver(clk_mt7622_hif_drv);