clk-mt7622-eth.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Chen Zhong <chen.zhong@mediatek.com>
  5. * Sean Wang <sean.wang@mediatek.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include "clk-mtk.h"
  13. #include "clk-gate.h"
  14. #include <dt-bindings/clock/mt7622-clk.h>
  15. #define GATE_ETH(_id, _name, _parent, _shift) { \
  16. .id = _id, \
  17. .name = _name, \
  18. .parent_name = _parent, \
  19. .regs = &eth_cg_regs, \
  20. .shift = _shift, \
  21. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  22. }
  23. static const struct mtk_gate_regs eth_cg_regs = {
  24. .set_ofs = 0x30,
  25. .clr_ofs = 0x30,
  26. .sta_ofs = 0x30,
  27. };
  28. static const struct mtk_gate eth_clks[] = {
  29. GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
  30. GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
  31. GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
  32. GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
  33. GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
  34. };
  35. static const struct mtk_gate_regs sgmii_cg_regs = {
  36. .set_ofs = 0xE4,
  37. .clr_ofs = 0xE4,
  38. .sta_ofs = 0xE4,
  39. };
  40. #define GATE_SGMII(_id, _name, _parent, _shift) { \
  41. .id = _id, \
  42. .name = _name, \
  43. .parent_name = _parent, \
  44. .regs = &sgmii_cg_regs, \
  45. .shift = _shift, \
  46. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  47. }
  48. static const struct mtk_gate sgmii_clks[] = {
  49. GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
  50. "ssusb_tx250m", 2),
  51. GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
  52. "ssusb_eq_rx250m", 3),
  53. GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
  54. "ssusb_cdr_ref", 4),
  55. GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
  56. "ssusb_cdr_fb", 5),
  57. };
  58. static int clk_mt7622_ethsys_init(struct platform_device *pdev)
  59. {
  60. struct clk_onecell_data *clk_data;
  61. struct device_node *node = pdev->dev.of_node;
  62. int r;
  63. clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
  64. mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
  65. clk_data);
  66. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  67. if (r)
  68. dev_err(&pdev->dev,
  69. "could not register clock provider: %s: %d\n",
  70. pdev->name, r);
  71. mtk_register_reset_controller(node, 1, 0x34);
  72. return r;
  73. }
  74. static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
  75. {
  76. struct clk_onecell_data *clk_data;
  77. struct device_node *node = pdev->dev.of_node;
  78. int r;
  79. clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
  80. mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
  81. clk_data);
  82. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  83. if (r)
  84. dev_err(&pdev->dev,
  85. "could not register clock provider: %s: %d\n",
  86. pdev->name, r);
  87. return r;
  88. }
  89. static const struct of_device_id of_match_clk_mt7622_eth[] = {
  90. {
  91. .compatible = "mediatek,mt7622-ethsys",
  92. .data = clk_mt7622_ethsys_init,
  93. }, {
  94. .compatible = "mediatek,mt7622-sgmiisys",
  95. .data = clk_mt7622_sgmiisys_init,
  96. }, {
  97. /* sentinel */
  98. }
  99. };
  100. static int clk_mt7622_eth_probe(struct platform_device *pdev)
  101. {
  102. int (*clk_init)(struct platform_device *);
  103. int r;
  104. clk_init = of_device_get_match_data(&pdev->dev);
  105. if (!clk_init)
  106. return -EINVAL;
  107. r = clk_init(pdev);
  108. if (r)
  109. dev_err(&pdev->dev,
  110. "could not register clock provider: %s: %d\n",
  111. pdev->name, r);
  112. return r;
  113. }
  114. static struct platform_driver clk_mt7622_eth_drv = {
  115. .probe = clk_mt7622_eth_probe,
  116. .driver = {
  117. .name = "clk-mt7622-eth",
  118. .of_match_table = of_match_clk_mt7622_eth,
  119. },
  120. };
  121. builtin_platform_driver(clk_mt7622_eth_drv);