clk-mt7622-aud.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Chen Zhong <chen.zhong@mediatek.com>
  5. * Sean Wang <sean.wang@mediatek.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/of.h>
  9. #include <linux/of_address.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include "clk-mtk.h"
  13. #include "clk-gate.h"
  14. #include <dt-bindings/clock/mt7622-clk.h>
  15. #define GATE_AUDIO0(_id, _name, _parent, _shift) { \
  16. .id = _id, \
  17. .name = _name, \
  18. .parent_name = _parent, \
  19. .regs = &audio0_cg_regs, \
  20. .shift = _shift, \
  21. .ops = &mtk_clk_gate_ops_no_setclr, \
  22. }
  23. #define GATE_AUDIO1(_id, _name, _parent, _shift) { \
  24. .id = _id, \
  25. .name = _name, \
  26. .parent_name = _parent, \
  27. .regs = &audio1_cg_regs, \
  28. .shift = _shift, \
  29. .ops = &mtk_clk_gate_ops_no_setclr, \
  30. }
  31. #define GATE_AUDIO2(_id, _name, _parent, _shift) { \
  32. .id = _id, \
  33. .name = _name, \
  34. .parent_name = _parent, \
  35. .regs = &audio2_cg_regs, \
  36. .shift = _shift, \
  37. .ops = &mtk_clk_gate_ops_no_setclr, \
  38. }
  39. #define GATE_AUDIO3(_id, _name, _parent, _shift) { \
  40. .id = _id, \
  41. .name = _name, \
  42. .parent_name = _parent, \
  43. .regs = &audio3_cg_regs, \
  44. .shift = _shift, \
  45. .ops = &mtk_clk_gate_ops_no_setclr, \
  46. }
  47. static const struct mtk_gate_regs audio0_cg_regs = {
  48. .set_ofs = 0x0,
  49. .clr_ofs = 0x0,
  50. .sta_ofs = 0x0,
  51. };
  52. static const struct mtk_gate_regs audio1_cg_regs = {
  53. .set_ofs = 0x10,
  54. .clr_ofs = 0x10,
  55. .sta_ofs = 0x10,
  56. };
  57. static const struct mtk_gate_regs audio2_cg_regs = {
  58. .set_ofs = 0x14,
  59. .clr_ofs = 0x14,
  60. .sta_ofs = 0x14,
  61. };
  62. static const struct mtk_gate_regs audio3_cg_regs = {
  63. .set_ofs = 0x634,
  64. .clr_ofs = 0x634,
  65. .sta_ofs = 0x634,
  66. };
  67. static const struct mtk_gate audio_clks[] = {
  68. /* AUDIO0 */
  69. GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
  70. GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
  71. GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
  72. GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
  73. /* AUDIO1 */
  74. GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
  75. GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
  76. GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
  77. GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
  78. GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
  79. GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
  80. GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
  81. GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
  82. GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
  83. GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
  84. GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
  85. GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
  86. GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
  87. GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
  88. GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
  89. GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23),
  90. /* AUDIO2 */
  91. GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
  92. GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
  93. GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
  94. GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
  95. GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
  96. GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
  97. GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
  98. GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
  99. GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
  100. GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
  101. GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
  102. GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
  103. GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
  104. GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
  105. GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
  106. GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
  107. GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
  108. GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
  109. /* AUDIO3 */
  110. GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
  111. GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
  112. GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
  113. GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
  114. GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
  115. GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
  116. GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
  117. GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
  118. GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
  119. };
  120. static int clk_mt7622_audiosys_init(struct platform_device *pdev)
  121. {
  122. struct clk_onecell_data *clk_data;
  123. struct device_node *node = pdev->dev.of_node;
  124. int r;
  125. clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
  126. mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
  127. clk_data);
  128. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  129. if (r) {
  130. dev_err(&pdev->dev,
  131. "could not register clock provider: %s: %d\n",
  132. pdev->name, r);
  133. goto err_clk_provider;
  134. }
  135. r = devm_of_platform_populate(&pdev->dev);
  136. if (r)
  137. goto err_plat_populate;
  138. return 0;
  139. err_plat_populate:
  140. of_clk_del_provider(node);
  141. err_clk_provider:
  142. return r;
  143. }
  144. static const struct of_device_id of_match_clk_mt7622_aud[] = {
  145. {
  146. .compatible = "mediatek,mt7622-audsys",
  147. .data = clk_mt7622_audiosys_init,
  148. }, {
  149. /* sentinel */
  150. }
  151. };
  152. static int clk_mt7622_aud_probe(struct platform_device *pdev)
  153. {
  154. int (*clk_init)(struct platform_device *);
  155. int r;
  156. clk_init = of_device_get_match_data(&pdev->dev);
  157. if (!clk_init)
  158. return -EINVAL;
  159. r = clk_init(pdev);
  160. if (r)
  161. dev_err(&pdev->dev,
  162. "could not register clock provider: %s: %d\n",
  163. pdev->name, r);
  164. return r;
  165. }
  166. static struct platform_driver clk_mt7622_aud_drv = {
  167. .probe = clk_mt7622_aud_probe,
  168. .driver = {
  169. .name = "clk-mt7622-aud",
  170. .of_match_table = of_match_clk_mt7622_aud,
  171. },
  172. };
  173. builtin_platform_driver(clk_mt7622_aud_drv);