clk-mt6797.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016 MediaTek Inc.
  4. * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
  5. */
  6. #include <linux/of.h>
  7. #include <linux/of_address.h>
  8. #include <linux/of_device.h>
  9. #include <linux/platform_device.h>
  10. #include "clk-mtk.h"
  11. #include "clk-gate.h"
  12. #include <dt-bindings/clock/mt6797-clk.h>
  13. /*
  14. * For some clocks, we don't care what their actual rates are. And these
  15. * clocks may change their rate on different products or different scenarios.
  16. * So we model these clocks' rate as 0, to denote it's not an actual rate.
  17. */
  18. static DEFINE_SPINLOCK(mt6797_clk_lock);
  19. static const struct mtk_fixed_factor top_fixed_divs[] = {
  20. FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
  21. FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  22. FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  23. FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  24. FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  25. FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  26. FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  27. FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
  28. FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  29. FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  30. FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  31. FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  32. FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  33. FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  34. FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  35. FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  36. FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  37. FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
  38. FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  39. FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
  40. FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
  41. FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
  42. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  43. FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
  44. FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
  45. FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
  46. FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  47. FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
  48. FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
  49. FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
  50. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  51. FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
  52. FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
  53. FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
  54. FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
  55. FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
  56. FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
  57. FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
  58. FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
  59. FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
  60. FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
  61. FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
  62. FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
  63. FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
  64. FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
  65. FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
  66. FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
  67. FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
  68. FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
  69. FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
  70. FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
  71. FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
  72. FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
  73. FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
  74. FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
  75. FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
  76. FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
  77. FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
  78. FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
  79. FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
  80. };
  81. static const char * const axi_parents[] = {
  82. "clk26m",
  83. "syspll_d7",
  84. "ulposc_axi_ck_mux",
  85. };
  86. static const char * const ulposc_axi_ck_mux_parents[] = {
  87. "syspll1_d4",
  88. "ulposc_axi_ck_mux_pre",
  89. };
  90. static const char * const ulposc_axi_ck_mux_pre_parents[] = {
  91. "ulposc_d2",
  92. "ulposc_d3",
  93. };
  94. static const char * const ddrphycfg_parents[] = {
  95. "clk26m",
  96. "syspll3_d2",
  97. "syspll2_d4",
  98. "syspll1_d8",
  99. };
  100. static const char * const mm_parents[] = {
  101. "clk26m",
  102. "imgpll_ck",
  103. "univpll1_d2",
  104. "syspll1_d2",
  105. };
  106. static const char * const pwm_parents[] = {
  107. "clk26m",
  108. "univpll2_d4",
  109. "ulposc_d2",
  110. "ulposc_d3",
  111. "ulposc_d8",
  112. "ulposc_d10",
  113. "ulposc_d4",
  114. };
  115. static const char * const vdec_parents[] = {
  116. "clk26m",
  117. "vdecpll_ck",
  118. "imgpll_ck",
  119. "syspll_d3",
  120. "univpll_d5",
  121. "clk26m",
  122. "clk26m",
  123. };
  124. static const char * const venc_parents[] = {
  125. "clk26m",
  126. "codecpll_ck",
  127. "syspll_d3",
  128. };
  129. static const char * const mfg_parents[] = {
  130. "clk26m",
  131. "mfgpll_ck",
  132. "syspll_d3",
  133. "univpll_d3",
  134. };
  135. static const char * const camtg[] = {
  136. "clk26m",
  137. "univpll_d26",
  138. "univpll2_d2",
  139. };
  140. static const char * const uart_parents[] = {
  141. "clk26m",
  142. "univpll2_d8",
  143. };
  144. static const char * const spi_parents[] = {
  145. "clk26m",
  146. "syspll3_d2",
  147. "syspll2_d4",
  148. "ulposc_spi_ck_mux",
  149. };
  150. static const char * const ulposc_spi_ck_mux_parents[] = {
  151. "ulposc_d2",
  152. "ulposc_d3",
  153. };
  154. static const char * const usb20_parents[] = {
  155. "clk26m",
  156. "univpll1_d8",
  157. "syspll4_d2",
  158. };
  159. static const char * const msdc50_0_hclk_parents[] = {
  160. "clk26m",
  161. "syspll1_d2",
  162. "syspll2_d2",
  163. "syspll4_d2",
  164. };
  165. static const char * const msdc50_0_parents[] = {
  166. "clk26m",
  167. "msdcpll",
  168. "syspll_d3",
  169. "univpll1_d4",
  170. "syspll2_d2",
  171. "syspll_d7",
  172. "msdcpll_d2",
  173. "univpll1_d2",
  174. "univpll_d3",
  175. };
  176. static const char * const msdc30_1_parents[] = {
  177. "clk26m",
  178. "univpll2_d2",
  179. "msdcpll_d2",
  180. "univpll1_d4",
  181. "syspll2_d2",
  182. "syspll_d7",
  183. "univpll_d7",
  184. };
  185. static const char * const msdc30_2_parents[] = {
  186. "clk26m",
  187. "univpll2_d8",
  188. "syspll2_d8",
  189. "syspll1_d8",
  190. "msdcpll_d8",
  191. "syspll3_d4",
  192. "univpll_d26",
  193. };
  194. static const char * const audio_parents[] = {
  195. "clk26m",
  196. "syspll3_d4",
  197. "syspll4_d4",
  198. "syspll1_d16",
  199. };
  200. static const char * const aud_intbus_parents[] = {
  201. "clk26m",
  202. "syspll1_d4",
  203. "syspll4_d2",
  204. };
  205. static const char * const pmicspi_parents[] = {
  206. "clk26m",
  207. "univpll_d26",
  208. "syspll3_d4",
  209. "syspll1_d8",
  210. "ulposc_d4",
  211. "ulposc_d8",
  212. "syspll2_d8",
  213. };
  214. static const char * const scp_parents[] = {
  215. "clk26m",
  216. "syspll_d3",
  217. "ulposc_ck",
  218. "univpll_d5",
  219. };
  220. static const char * const atb_parents[] = {
  221. "clk26m",
  222. "syspll1_d2",
  223. "syspll_d5",
  224. };
  225. static const char * const mjc_parents[] = {
  226. "clk26m",
  227. "imgpll_ck",
  228. "univpll_d5",
  229. "syspll1_d2",
  230. };
  231. static const char * const dpi0_parents[] = {
  232. "clk26m",
  233. "tvdpll_d2",
  234. "tvdpll_d4",
  235. "tvdpll_d8",
  236. "tvdpll_d16",
  237. "clk26m",
  238. "clk26m",
  239. };
  240. static const char * const aud_1_parents[] = {
  241. "clk26m",
  242. "apll1_ck",
  243. };
  244. static const char * const aud_2_parents[] = {
  245. "clk26m",
  246. "apll2_ck",
  247. };
  248. static const char * const ssusb_top_sys_parents[] = {
  249. "clk26m",
  250. "univpll3_d2",
  251. };
  252. static const char * const spm_parents[] = {
  253. "clk26m",
  254. "syspll1_d8",
  255. };
  256. static const char * const bsi_spi_parents[] = {
  257. "clk26m",
  258. "syspll_d3_d3",
  259. "syspll1_d4",
  260. "syspll_d7",
  261. };
  262. static const char * const audio_h_parents[] = {
  263. "clk26m",
  264. "apll2_ck",
  265. "apll1_ck",
  266. "univpll_d7",
  267. };
  268. static const char * const mfg_52m_parents[] = {
  269. "clk26m",
  270. "univpll2_d8",
  271. "univpll2_d4",
  272. "univpll2_d4",
  273. };
  274. static const char * const anc_md32_parents[] = {
  275. "clk26m",
  276. "syspll1_d2",
  277. "univpll_d5",
  278. };
  279. /*
  280. * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
  281. * critical as otherwise the system will hang after boot.
  282. */
  283. static const struct mtk_composite top_muxes[] = {
  284. MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
  285. ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
  286. MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
  287. ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
  288. MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
  289. 0x0040, 0, 2),
  290. MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
  291. 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
  292. MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
  293. 0x0040, 24, 2),
  294. MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
  295. MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
  296. MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
  297. MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
  298. MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
  299. MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
  300. MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
  301. MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
  302. ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
  303. MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
  304. 0x0060, 24, 2, 31),
  305. MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
  306. msdc50_0_hclk_parents, 0x0070, 8, 2),
  307. MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
  308. 0x0070, 16, 4, 23),
  309. MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
  310. 0x0070, 24, 3, 31),
  311. MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
  312. 0x0080, 0, 3, 7),
  313. MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
  314. 0x0080, 16, 2, 23),
  315. MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
  316. 0x0080, 24, 2),
  317. MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
  318. 0x0090, 0, 3),
  319. MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
  320. 0x0090, 8, 2),
  321. MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
  322. 0x0090, 16, 2),
  323. MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
  324. MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
  325. MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
  326. 0x00A0, 16, 1, 23),
  327. MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
  328. 0x00A0, 24, 1, 31),
  329. MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
  330. ssusb_top_sys_parents, 0x00B0, 8, 1),
  331. MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
  332. 0x00C0, 0, 1),
  333. MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
  334. 0x00C0, 8, 2),
  335. MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
  336. 0x00C0, 16, 2, 23),
  337. MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
  338. 0x00C0, 24, 2, 31),
  339. MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
  340. 0x0104, 1, 2),
  341. };
  342. static int mtk_topckgen_init(struct platform_device *pdev)
  343. {
  344. struct clk_onecell_data *clk_data;
  345. void __iomem *base;
  346. struct device_node *node = pdev->dev.of_node;
  347. base = devm_platform_ioremap_resource(pdev, 0);
  348. if (IS_ERR(base))
  349. return PTR_ERR(base);
  350. clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
  351. mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
  352. clk_data);
  353. mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
  354. &mt6797_clk_lock, clk_data);
  355. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  356. }
  357. static const struct mtk_gate_regs infra0_cg_regs = {
  358. .set_ofs = 0x0080,
  359. .clr_ofs = 0x0084,
  360. .sta_ofs = 0x0090,
  361. };
  362. static const struct mtk_gate_regs infra1_cg_regs = {
  363. .set_ofs = 0x0088,
  364. .clr_ofs = 0x008c,
  365. .sta_ofs = 0x0094,
  366. };
  367. static const struct mtk_gate_regs infra2_cg_regs = {
  368. .set_ofs = 0x00a8,
  369. .clr_ofs = 0x00ac,
  370. .sta_ofs = 0x00b0,
  371. };
  372. #define GATE_ICG0(_id, _name, _parent, _shift) { \
  373. .id = _id, \
  374. .name = _name, \
  375. .parent_name = _parent, \
  376. .regs = &infra0_cg_regs, \
  377. .shift = _shift, \
  378. .ops = &mtk_clk_gate_ops_setclr, \
  379. }
  380. #define GATE_ICG1(_id, _name, _parent, _shift) \
  381. GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
  382. #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
  383. .id = _id, \
  384. .name = _name, \
  385. .parent_name = _parent, \
  386. .regs = &infra1_cg_regs, \
  387. .shift = _shift, \
  388. .ops = &mtk_clk_gate_ops_setclr, \
  389. .flags = _flags, \
  390. }
  391. #define GATE_ICG2(_id, _name, _parent, _shift) \
  392. GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
  393. #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
  394. .id = _id, \
  395. .name = _name, \
  396. .parent_name = _parent, \
  397. .regs = &infra2_cg_regs, \
  398. .shift = _shift, \
  399. .ops = &mtk_clk_gate_ops_setclr, \
  400. .flags = _flags, \
  401. }
  402. /*
  403. * Clock gates dramc and dramc_b are needed by the DRAM controller.
  404. * We mark them as critical as otherwise the system will hang after boot.
  405. */
  406. static const struct mtk_gate infra_clks[] = {
  407. GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
  408. GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
  409. GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
  410. GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
  411. GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
  412. GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
  413. GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
  414. GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
  415. GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
  416. GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
  417. GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
  418. GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
  419. GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
  420. GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
  421. GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
  422. GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
  423. GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
  424. GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
  425. GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
  426. GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
  427. GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
  428. GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
  429. GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
  430. GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
  431. GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
  432. GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
  433. GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
  434. GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
  435. GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
  436. GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
  437. GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
  438. GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
  439. GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
  440. GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
  441. GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
  442. GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
  443. GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
  444. GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
  445. GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
  446. GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
  447. GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
  448. GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
  449. "axi_sel", 12),
  450. GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
  451. "axi_sel", 13),
  452. GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
  453. GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
  454. GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
  455. GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
  456. GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
  457. GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
  458. GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
  459. GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
  460. GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
  461. "clk26m", 31, CLK_IS_CRITICAL),
  462. GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
  463. GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
  464. GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
  465. GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
  466. GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
  467. GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
  468. GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
  469. GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
  470. GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
  471. GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
  472. GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
  473. "clk26m", 11, CLK_IS_CRITICAL),
  474. GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
  475. GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
  476. GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
  477. GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
  478. GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
  479. GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
  480. GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
  481. GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
  482. GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
  483. GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
  484. GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
  485. GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
  486. "ssusb_top_sys_sel", 24),
  487. GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
  488. GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
  489. GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
  490. "clk26m", 27),
  491. GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
  492. "axi_sel", 28),
  493. GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
  494. GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
  495. GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
  496. GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
  497. };
  498. static const struct mtk_fixed_factor infra_fixed_divs[] = {
  499. FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
  500. };
  501. static struct clk_onecell_data *infra_clk_data;
  502. static void mtk_infrasys_init_early(struct device_node *node)
  503. {
  504. int r, i;
  505. if (!infra_clk_data) {
  506. infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
  507. for (i = 0; i < CLK_INFRA_NR; i++)
  508. infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
  509. }
  510. mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
  511. infra_clk_data);
  512. r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
  513. if (r)
  514. pr_err("%s(): could not register clock provider: %d\n",
  515. __func__, r);
  516. }
  517. CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
  518. mtk_infrasys_init_early);
  519. static int mtk_infrasys_init(struct platform_device *pdev)
  520. {
  521. int i;
  522. struct device_node *node = pdev->dev.of_node;
  523. if (!infra_clk_data) {
  524. infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
  525. } else {
  526. for (i = 0; i < CLK_INFRA_NR; i++) {
  527. if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
  528. infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
  529. }
  530. }
  531. mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  532. infra_clk_data);
  533. mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
  534. infra_clk_data);
  535. return of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
  536. }
  537. #define MT6797_PLL_FMAX (3000UL * MHZ)
  538. #define CON0_MT6797_RST_BAR BIT(24)
  539. #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  540. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
  541. _pcw_shift, _div_table) { \
  542. .id = _id, \
  543. .name = _name, \
  544. .reg = _reg, \
  545. .pwr_reg = _pwr_reg, \
  546. .en_mask = _en_mask, \
  547. .flags = _flags, \
  548. .rst_bar_mask = CON0_MT6797_RST_BAR, \
  549. .fmax = MT6797_PLL_FMAX, \
  550. .pcwbits = _pcwbits, \
  551. .pd_reg = _pd_reg, \
  552. .pd_shift = _pd_shift, \
  553. .tuner_reg = _tuner_reg, \
  554. .pcw_reg = _pcw_reg, \
  555. .pcw_shift = _pcw_shift, \
  556. .div_table = _div_table, \
  557. }
  558. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  559. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
  560. _pcw_shift) \
  561. PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  562. _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
  563. NULL)
  564. static const struct mtk_pll_data plls[] = {
  565. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
  566. 21, 0x220, 4, 0x0, 0x224, 0),
  567. PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
  568. 0x230, 4, 0x0, 0x234, 14),
  569. PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
  570. 0x244, 24, 0x0, 0x244, 0),
  571. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
  572. 0x250, 4, 0x0, 0x254, 0),
  573. PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
  574. 0x260, 4, 0x0, 0x264, 0),
  575. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
  576. 0x270, 4, 0x0, 0x274, 0),
  577. PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
  578. 0x290, 4, 0x0, 0x294, 0),
  579. PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
  580. 0x2E4, 4, 0x0, 0x2E8, 0),
  581. PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
  582. 0x2A0, 4, 0x2A8, 0x2A4, 0),
  583. PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
  584. 0x2B4, 4, 0x2BC, 0x2B8, 0),
  585. };
  586. static int mtk_apmixedsys_init(struct platform_device *pdev)
  587. {
  588. struct clk_onecell_data *clk_data;
  589. struct device_node *node = pdev->dev.of_node;
  590. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
  591. if (!clk_data)
  592. return -ENOMEM;
  593. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  594. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  595. }
  596. static const struct of_device_id of_match_clk_mt6797[] = {
  597. {
  598. .compatible = "mediatek,mt6797-topckgen",
  599. .data = mtk_topckgen_init,
  600. }, {
  601. .compatible = "mediatek,mt6797-infracfg",
  602. .data = mtk_infrasys_init,
  603. }, {
  604. .compatible = "mediatek,mt6797-apmixedsys",
  605. .data = mtk_apmixedsys_init,
  606. }, {
  607. /* sentinel */
  608. }
  609. };
  610. static int clk_mt6797_probe(struct platform_device *pdev)
  611. {
  612. int (*clk_init)(struct platform_device *);
  613. int r;
  614. clk_init = of_device_get_match_data(&pdev->dev);
  615. if (!clk_init)
  616. return -EINVAL;
  617. r = clk_init(pdev);
  618. if (r)
  619. dev_err(&pdev->dev,
  620. "could not register clock provider: %s: %d\n",
  621. pdev->name, r);
  622. return r;
  623. }
  624. static struct platform_driver clk_mt6797_drv = {
  625. .probe = clk_mt6797_probe,
  626. .driver = {
  627. .name = "clk-mt6797",
  628. .of_match_table = of_match_clk_mt6797,
  629. },
  630. };
  631. static int __init clk_mt6797_init(void)
  632. {
  633. return platform_driver_register(&clk_mt6797_drv);
  634. }
  635. arch_initcall(clk_mt6797_init);