clk-mt6797-mm.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include <dt-bindings/clock/mt6797-clk.h>
  9. #include "clk-mtk.h"
  10. #include "clk-gate.h"
  11. static const struct mtk_gate_regs mm0_cg_regs = {
  12. .set_ofs = 0x0104,
  13. .clr_ofs = 0x0108,
  14. .sta_ofs = 0x0100,
  15. };
  16. static const struct mtk_gate_regs mm1_cg_regs = {
  17. .set_ofs = 0x0114,
  18. .clr_ofs = 0x0118,
  19. .sta_ofs = 0x0110,
  20. };
  21. #define GATE_MM0(_id, _name, _parent, _shift) { \
  22. .id = _id, \
  23. .name = _name, \
  24. .parent_name = _parent, \
  25. .regs = &mm0_cg_regs, \
  26. .shift = _shift, \
  27. .ops = &mtk_clk_gate_ops_setclr, \
  28. }
  29. #define GATE_MM1(_id, _name, _parent, _shift) { \
  30. .id = _id, \
  31. .name = _name, \
  32. .parent_name = _parent, \
  33. .regs = &mm1_cg_regs, \
  34. .shift = _shift, \
  35. .ops = &mtk_clk_gate_ops_setclr, \
  36. }
  37. static const struct mtk_gate mm_clks[] = {
  38. GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
  39. GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
  40. GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),
  41. GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),
  42. GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),
  43. GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),
  44. GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),
  45. GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),
  46. GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),
  47. GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
  48. GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),
  49. GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
  50. GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
  51. GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
  52. GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
  53. GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),
  54. GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),
  55. GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),
  56. GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),
  57. GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),
  58. GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),
  59. GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
  60. GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
  61. GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),
  62. GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),
  63. GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
  64. GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
  65. GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),
  66. GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),
  67. GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),
  68. GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),
  69. GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
  70. GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),
  71. GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),
  72. GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),
  73. GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",
  74. "dpi0_sel", 5),
  75. GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",
  76. "mm_sel", 6),
  77. GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",
  78. "mjc_sel", 7),
  79. GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",
  80. "mm_sel", 8),
  81. GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),
  82. GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",
  83. "clk26m", 1),
  84. GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",
  85. "clk26m", 3),
  86. };
  87. static int clk_mt6797_mm_probe(struct platform_device *pdev)
  88. {
  89. struct device *dev = &pdev->dev;
  90. struct device_node *node = dev->parent->of_node;
  91. struct clk_onecell_data *clk_data;
  92. int r;
  93. clk_data = mtk_alloc_clk_data(CLK_MM_NR);
  94. mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
  95. clk_data);
  96. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  97. if (r)
  98. dev_err(&pdev->dev,
  99. "could not register clock provider: %s: %d\n",
  100. pdev->name, r);
  101. return r;
  102. }
  103. static struct platform_driver clk_mt6797_mm_drv = {
  104. .probe = clk_mt6797_mm_probe,
  105. .driver = {
  106. .name = "clk-mt6797-mm",
  107. },
  108. };
  109. builtin_platform_driver(clk_mt6797_mm_drv);