clk-mt6779.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. * Author: Wendell Lin <wendell.lin@mediatek.com>
  5. */
  6. #include <linux/of.h>
  7. #include <linux/of_address.h>
  8. #include <linux/of_device.h>
  9. #include <linux/platform_device.h>
  10. #include "clk-mtk.h"
  11. #include "clk-mux.h"
  12. #include "clk-gate.h"
  13. #include <dt-bindings/clock/mt6779-clk.h>
  14. static DEFINE_SPINLOCK(mt6779_clk_lock);
  15. static const struct mtk_fixed_clk top_fixed_clks[] = {
  16. FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
  17. };
  18. static const struct mtk_fixed_factor top_divs[] = {
  19. FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
  20. FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
  21. FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
  22. FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
  23. FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
  24. FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
  25. FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
  26. FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
  27. FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
  28. FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
  29. FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
  30. FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
  31. FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
  32. FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
  33. FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
  34. FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
  35. FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
  36. FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
  37. FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
  38. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  39. FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
  40. FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
  41. FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
  42. FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  43. FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
  44. FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
  45. FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
  46. FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
  47. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  48. FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
  49. FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
  50. FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
  51. FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  52. FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
  53. FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
  54. 1, 2),
  55. FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
  56. 1, 4),
  57. FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
  58. 1, 8),
  59. FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
  60. 1, 16),
  61. FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
  62. 1, 32),
  63. FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
  64. FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
  65. FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
  66. FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
  67. FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
  68. FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
  69. FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
  70. FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
  71. FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
  72. FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
  73. FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
  74. FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
  75. FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
  76. FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
  77. FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
  78. FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
  79. FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
  80. FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
  81. FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
  82. FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
  83. FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
  84. FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
  85. FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
  86. FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
  87. FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
  88. FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
  89. FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
  90. FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
  91. FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  92. FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
  93. FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
  94. FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
  95. FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
  96. FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
  97. FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
  98. FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
  99. FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
  100. FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
  101. FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
  102. FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
  103. FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
  104. FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
  105. "tvdpll", 1, 1),
  106. FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
  107. };
  108. static const char * const axi_parents[] = {
  109. "clk26m",
  110. "mainpll_d2_d4",
  111. "mainpll_d7",
  112. "osc_d4"
  113. };
  114. static const char * const mm_parents[] = {
  115. "clk26m",
  116. "tvdpll_mainpll_d2_ck",
  117. "mmpll_d7",
  118. "mmpll_d5_d2",
  119. "mainpll_d2_d2",
  120. "mainpll_d3_d2"
  121. };
  122. static const char * const scp_parents[] = {
  123. "clk26m",
  124. "univpll_d2_d8",
  125. "mainpll_d2_d4",
  126. "mainpll_d3",
  127. "univpll_d3",
  128. "ad_osc2_ck",
  129. "osc2_d2",
  130. "osc2_d3"
  131. };
  132. static const char * const img_parents[] = {
  133. "clk26m",
  134. "mainpll_d2",
  135. "mainpll_d2",
  136. "univpll_d3",
  137. "mainpll_d3",
  138. "mmpll_d5_d2",
  139. "tvdpll_mainpll_d2_ck",
  140. "mainpll_d5"
  141. };
  142. static const char * const ipe_parents[] = {
  143. "clk26m",
  144. "mainpll_d2",
  145. "mmpll_d7",
  146. "univpll_d3",
  147. "mainpll_d3",
  148. "mmpll_d5_d2",
  149. "mainpll_d2_d2",
  150. "mainpll_d5"
  151. };
  152. static const char * const dpe_parents[] = {
  153. "clk26m",
  154. "mainpll_d2",
  155. "mmpll_d7",
  156. "univpll_d3",
  157. "mainpll_d3",
  158. "mmpll_d5_d2",
  159. "mainpll_d2_d2",
  160. "mainpll_d5"
  161. };
  162. static const char * const cam_parents[] = {
  163. "clk26m",
  164. "mainpll_d2",
  165. "mmpll_d6",
  166. "mainpll_d3",
  167. "mmpll_d7",
  168. "univpll_d3",
  169. "mmpll_d5_d2",
  170. "adsppll_d5",
  171. "tvdpll_mainpll_d2_ck",
  172. "univpll_d3_d2"
  173. };
  174. static const char * const ccu_parents[] = {
  175. "clk26m",
  176. "mainpll_d2",
  177. "mmpll_d6",
  178. "mainpll_d3",
  179. "mmpll_d7",
  180. "univpll_d3",
  181. "mmpll_d5_d2",
  182. "mainpll_d2_d2",
  183. "adsppll_d5",
  184. "univpll_d3_d2"
  185. };
  186. static const char * const dsp_parents[] = {
  187. "clk26m",
  188. "univpll_d3_d8",
  189. "univpll_d3_d4",
  190. "mainpll_d2_d4",
  191. "univpll_d3_d2",
  192. "mainpll_d2_d2",
  193. "univpll_d2_d2",
  194. "mainpll_d3",
  195. "univpll_d3",
  196. "mmpll_d7",
  197. "mmpll_d6",
  198. "adsppll_d5",
  199. "tvdpll_ck",
  200. "tvdpll_mainpll_d2_ck",
  201. "univpll_d2",
  202. "adsppll_d4"
  203. };
  204. static const char * const dsp1_parents[] = {
  205. "clk26m",
  206. "univpll_d3_d8",
  207. "univpll_d3_d4",
  208. "mainpll_d2_d4",
  209. "univpll_d3_d2",
  210. "mainpll_d2_d2",
  211. "univpll_d2_d2",
  212. "mainpll_d3",
  213. "univpll_d3",
  214. "mmpll_d7",
  215. "mmpll_d6",
  216. "adsppll_d5",
  217. "tvdpll_ck",
  218. "tvdpll_mainpll_d2_ck",
  219. "univpll_d2",
  220. "adsppll_d4"
  221. };
  222. static const char * const dsp2_parents[] = {
  223. "clk26m",
  224. "univpll_d3_d8",
  225. "univpll_d3_d4",
  226. "mainpll_d2_d4",
  227. "univpll_d3_d2",
  228. "mainpll_d2_d2",
  229. "univpll_d2_d2",
  230. "mainpll_d3",
  231. "univpll_d3",
  232. "mmpll_d7",
  233. "mmpll_d6",
  234. "adsppll_d5",
  235. "tvdpll_ck",
  236. "tvdpll_mainpll_d2_ck",
  237. "univpll_d2",
  238. "adsppll_d4"
  239. };
  240. static const char * const dsp3_parents[] = {
  241. "clk26m",
  242. "univpll_d3_d8",
  243. "mainpll_d2_d4",
  244. "univpll_d3_d2",
  245. "mainpll_d2_d2",
  246. "univpll_d2_d2",
  247. "mainpll_d3",
  248. "univpll_d3",
  249. "mmpll_d7",
  250. "mmpll_d6",
  251. "mainpll_d2",
  252. "tvdpll_ck",
  253. "tvdpll_mainpll_d2_ck",
  254. "univpll_d2",
  255. "adsppll_d4",
  256. "mmpll_d4"
  257. };
  258. static const char * const ipu_if_parents[] = {
  259. "clk26m",
  260. "univpll_d3_d8",
  261. "univpll_d3_d4",
  262. "mainpll_d2_d4",
  263. "univpll_d3_d2",
  264. "mainpll_d2_d2",
  265. "univpll_d2_d2",
  266. "mainpll_d3",
  267. "univpll_d3",
  268. "mmpll_d7",
  269. "mmpll_d6",
  270. "adsppll_d5",
  271. "tvdpll_ck",
  272. "tvdpll_mainpll_d2_ck",
  273. "univpll_d2",
  274. "adsppll_d4"
  275. };
  276. static const char * const mfg_parents[] = {
  277. "clk26m",
  278. "mfgpll_ck",
  279. "univpll_d3",
  280. "mainpll_d5"
  281. };
  282. static const char * const f52m_mfg_parents[] = {
  283. "clk26m",
  284. "univpll_d3_d2",
  285. "univpll_d3_d4",
  286. "univpll_d3_d8"
  287. };
  288. static const char * const camtg_parents[] = {
  289. "clk26m",
  290. "univpll_192m_d8",
  291. "univpll_d3_d8",
  292. "univpll_192m_d4",
  293. "univpll_d3_d16",
  294. "csw_f26m_ck_d2",
  295. "univpll_192m_d16",
  296. "univpll_192m_d32"
  297. };
  298. static const char * const camtg2_parents[] = {
  299. "clk26m",
  300. "univpll_192m_d8",
  301. "univpll_d3_d8",
  302. "univpll_192m_d4",
  303. "univpll_d3_d16",
  304. "csw_f26m_ck_d2",
  305. "univpll_192m_d16",
  306. "univpll_192m_d32"
  307. };
  308. static const char * const camtg3_parents[] = {
  309. "clk26m",
  310. "univpll_192m_d8",
  311. "univpll_d3_d8",
  312. "univpll_192m_d4",
  313. "univpll_d3_d16",
  314. "csw_f26m_ck_d2",
  315. "univpll_192m_d16",
  316. "univpll_192m_d32"
  317. };
  318. static const char * const camtg4_parents[] = {
  319. "clk26m",
  320. "univpll_192m_d8",
  321. "univpll_d3_d8",
  322. "univpll_192m_d4",
  323. "univpll_d3_d16",
  324. "csw_f26m_ck_d2",
  325. "univpll_192m_d16",
  326. "univpll_192m_d32"
  327. };
  328. static const char * const uart_parents[] = {
  329. "clk26m",
  330. "univpll_d3_d8"
  331. };
  332. static const char * const spi_parents[] = {
  333. "clk26m",
  334. "mainpll_d5_d2",
  335. "mainpll_d3_d4",
  336. "msdcpll_d4"
  337. };
  338. static const char * const msdc50_hclk_parents[] = {
  339. "clk26m",
  340. "mainpll_d2_d2",
  341. "mainpll_d3_d2"
  342. };
  343. static const char * const msdc50_0_parents[] = {
  344. "clk26m",
  345. "msdcpll_ck",
  346. "msdcpll_d2",
  347. "univpll_d2_d4",
  348. "mainpll_d3_d2",
  349. "univpll_d2_d2"
  350. };
  351. static const char * const msdc30_1_parents[] = {
  352. "clk26m",
  353. "univpll_d3_d2",
  354. "mainpll_d3_d2",
  355. "mainpll_d7",
  356. "msdcpll_d2"
  357. };
  358. static const char * const audio_parents[] = {
  359. "clk26m",
  360. "mainpll_d5_d4",
  361. "mainpll_d7_d4",
  362. "mainpll_d2_d16"
  363. };
  364. static const char * const aud_intbus_parents[] = {
  365. "clk26m",
  366. "mainpll_d2_d4",
  367. "mainpll_d7_d2"
  368. };
  369. static const char * const fpwrap_ulposc_parents[] = {
  370. "osc_d10",
  371. "clk26m",
  372. "osc_d4",
  373. "osc_d8",
  374. "osc_d16"
  375. };
  376. static const char * const atb_parents[] = {
  377. "clk26m",
  378. "mainpll_d2_d2",
  379. "mainpll_d5"
  380. };
  381. static const char * const sspm_parents[] = {
  382. "clk26m",
  383. "univpll_d2_d4",
  384. "mainpll_d2_d2",
  385. "univpll_d2_d2",
  386. "mainpll_d3"
  387. };
  388. static const char * const dpi0_parents[] = {
  389. "clk26m",
  390. "tvdpll_d2",
  391. "tvdpll_d4",
  392. "tvdpll_d8",
  393. "tvdpll_d16"
  394. };
  395. static const char * const scam_parents[] = {
  396. "clk26m",
  397. "mainpll_d5_d2"
  398. };
  399. static const char * const disppwm_parents[] = {
  400. "clk26m",
  401. "univpll_d3_d4",
  402. "osc_d2",
  403. "osc_d4",
  404. "osc_d16"
  405. };
  406. static const char * const usb_top_parents[] = {
  407. "clk26m",
  408. "univpll_d5_d4",
  409. "univpll_d3_d4",
  410. "univpll_d5_d2"
  411. };
  412. static const char * const ssusb_top_xhci_parents[] = {
  413. "clk26m",
  414. "univpll_d5_d4",
  415. "univpll_d3_d4",
  416. "univpll_d5_d2"
  417. };
  418. static const char * const spm_parents[] = {
  419. "clk26m",
  420. "osc_d8",
  421. "mainpll_d2_d8"
  422. };
  423. static const char * const i2c_parents[] = {
  424. "clk26m",
  425. "mainpll_d2_d8",
  426. "univpll_d5_d2"
  427. };
  428. static const char * const seninf_parents[] = {
  429. "clk26m",
  430. "univpll_d7",
  431. "univpll_d3_d2",
  432. "univpll_d2_d2",
  433. "mainpll_d3",
  434. "mmpll_d4_d2",
  435. "mmpll_d7",
  436. "mmpll_d6"
  437. };
  438. static const char * const seninf1_parents[] = {
  439. "clk26m",
  440. "univpll_d7",
  441. "univpll_d3_d2",
  442. "univpll_d2_d2",
  443. "mainpll_d3",
  444. "mmpll_d4_d2",
  445. "mmpll_d7",
  446. "mmpll_d6"
  447. };
  448. static const char * const seninf2_parents[] = {
  449. "clk26m",
  450. "univpll_d7",
  451. "univpll_d3_d2",
  452. "univpll_d2_d2",
  453. "mainpll_d3",
  454. "mmpll_d4_d2",
  455. "mmpll_d7",
  456. "mmpll_d6"
  457. };
  458. static const char * const dxcc_parents[] = {
  459. "clk26m",
  460. "mainpll_d2_d2",
  461. "mainpll_d2_d4",
  462. "mainpll_d2_d8"
  463. };
  464. static const char * const aud_engen1_parents[] = {
  465. "clk26m",
  466. "apll1_d2",
  467. "apll1_d4",
  468. "apll1_d8"
  469. };
  470. static const char * const aud_engen2_parents[] = {
  471. "clk26m",
  472. "apll2_d2",
  473. "apll2_d4",
  474. "apll2_d8"
  475. };
  476. static const char * const faes_ufsfde_parents[] = {
  477. "clk26m",
  478. "mainpll_d2",
  479. "mainpll_d2_d2",
  480. "mainpll_d3",
  481. "mainpll_d2_d4",
  482. "univpll_d3"
  483. };
  484. static const char * const fufs_parents[] = {
  485. "clk26m",
  486. "mainpll_d2_d4",
  487. "mainpll_d2_d8",
  488. "mainpll_d2_d16"
  489. };
  490. static const char * const aud_1_parents[] = {
  491. "clk26m",
  492. "apll1_ck"
  493. };
  494. static const char * const aud_2_parents[] = {
  495. "clk26m",
  496. "apll2_ck"
  497. };
  498. static const char * const adsp_parents[] = {
  499. "clk26m",
  500. "mainpll_d3",
  501. "univpll_d2_d4",
  502. "univpll_d2",
  503. "mmpll_d4",
  504. "adsppll_d4",
  505. "adsppll_d6"
  506. };
  507. static const char * const dpmaif_parents[] = {
  508. "clk26m",
  509. "univpll_d2_d4",
  510. "mainpll_d3",
  511. "mainpll_d2_d2",
  512. "univpll_d2_d2",
  513. "univpll_d3"
  514. };
  515. static const char * const venc_parents[] = {
  516. "clk26m",
  517. "mmpll_d7",
  518. "mainpll_d3",
  519. "univpll_d2_d2",
  520. "mainpll_d2_d2",
  521. "univpll_d3",
  522. "mmpll_d6",
  523. "mainpll_d5",
  524. "mainpll_d3_d2",
  525. "mmpll_d4_d2",
  526. "univpll_d2_d4",
  527. "mmpll_d5",
  528. "univpll_192m_d2"
  529. };
  530. static const char * const vdec_parents[] = {
  531. "clk26m",
  532. "univpll_d2_d4",
  533. "mainpll_d3",
  534. "univpll_d2_d2",
  535. "mainpll_d2_d2",
  536. "univpll_d3",
  537. "univpll_d5",
  538. "univpll_d5_d2",
  539. "mainpll_d2",
  540. "univpll_d2",
  541. "univpll_192m_d2"
  542. };
  543. static const char * const camtm_parents[] = {
  544. "clk26m",
  545. "univpll_d7",
  546. "univpll_d3_d2",
  547. "univpll_d2_d2"
  548. };
  549. static const char * const pwm_parents[] = {
  550. "clk26m",
  551. "univpll_d2_d8"
  552. };
  553. static const char * const audio_h_parents[] = {
  554. "clk26m",
  555. "univpll_d7",
  556. "apll1_ck",
  557. "apll2_ck"
  558. };
  559. static const char * const camtg5_parents[] = {
  560. "clk26m",
  561. "univpll_192m_d8",
  562. "univpll_d3_d8",
  563. "univpll_192m_d4",
  564. "univpll_d3_d16",
  565. "csw_f26m_ck_d2",
  566. "univpll_192m_d16",
  567. "univpll_192m_d32"
  568. };
  569. /*
  570. * CRITICAL CLOCK:
  571. * axi_sel is the main bus clock of whole SOC.
  572. * spm_sel is the clock of the always-on co-processor.
  573. * sspm_sel is the clock of the always-on co-processor.
  574. */
  575. static const struct mtk_mux top_muxes[] = {
  576. /* CLK_CFG_0 */
  577. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
  578. 0x20, 0x24, 0x28, 0, 2, 7,
  579. 0x004, 0, CLK_IS_CRITICAL),
  580. MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
  581. 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
  582. MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
  583. 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
  584. /* CLK_CFG_1 */
  585. MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
  586. 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
  587. MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
  588. 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
  589. MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
  590. 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
  591. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
  592. 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
  593. /* CLK_CFG_2 */
  594. MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
  595. 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
  596. MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
  597. 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
  598. MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
  599. 0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
  600. MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
  601. 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
  602. /* CLK_CFG_3 */
  603. MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
  604. 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
  605. MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
  606. 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
  607. MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
  608. 0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
  609. MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
  610. f52m_mfg_parents, 0x50, 0x54, 0x58,
  611. 24, 2, 31, 0x004, 15),
  612. /* CLK_CFG_4 */
  613. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
  614. 0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
  615. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
  616. 0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
  617. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
  618. 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
  619. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
  620. 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
  621. /* CLK_CFG_5 */
  622. MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
  623. 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
  624. MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
  625. 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
  626. MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
  627. msdc50_hclk_parents, 0x70, 0x74, 0x78,
  628. 16, 2, 23, 0x004, 22),
  629. MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
  630. msdc50_0_parents, 0x70, 0x74, 0x78,
  631. 24, 3, 31, 0x004, 23),
  632. /* CLK_CFG_6 */
  633. MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
  634. msdc30_1_parents, 0x80, 0x84, 0x88,
  635. 0, 3, 7, 0x004, 24),
  636. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
  637. 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
  638. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
  639. aud_intbus_parents, 0x80, 0x84, 0x88,
  640. 16, 2, 23, 0x004, 26),
  641. MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
  642. fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
  643. 24, 3, 31, 0x004, 27),
  644. /* CLK_CFG_7 */
  645. MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
  646. 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
  647. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
  648. 0x90, 0x94, 0x98, 8, 3, 15,
  649. 0x004, 29, CLK_IS_CRITICAL),
  650. MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
  651. 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
  652. MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
  653. 0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
  654. /* CLK_CFG_8 */
  655. MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
  656. disppwm_parents, 0xa0, 0xa4, 0xa8,
  657. 0, 3, 7, 0x008, 1),
  658. MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
  659. usb_top_parents, 0xa0, 0xa4, 0xa8,
  660. 8, 2, 15, 0x008, 2),
  661. MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
  662. ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
  663. 16, 2, 23, 0x008, 3),
  664. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
  665. 0xa0, 0xa4, 0xa8, 24, 2, 31,
  666. 0x008, 4, CLK_IS_CRITICAL),
  667. /* CLK_CFG_9 */
  668. MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
  669. 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
  670. MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
  671. 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
  672. MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
  673. seninf1_parents, 0xb0, 0xb4, 0xb8,
  674. 16, 2, 23, 0x008, 7),
  675. MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
  676. seninf2_parents, 0xb0, 0xb4, 0xb8,
  677. 24, 2, 31, 0x008, 8),
  678. /* CLK_CFG_10 */
  679. MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
  680. 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
  681. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
  682. aud_engen1_parents, 0xc0, 0xc4, 0xc8,
  683. 8, 2, 15, 0x008, 10),
  684. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
  685. aud_engen2_parents, 0xc0, 0xc4, 0xc8,
  686. 16, 2, 23, 0x008, 11),
  687. MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
  688. faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
  689. 24, 3, 31,
  690. 0x008, 12),
  691. /* CLK_CFG_11 */
  692. MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
  693. 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
  694. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
  695. 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
  696. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
  697. 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
  698. MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
  699. 0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
  700. /* CLK_CFG_12 */
  701. MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
  702. 0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
  703. MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
  704. 0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
  705. MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
  706. 0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
  707. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
  708. 0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
  709. /* CLK_CFG_13 */
  710. MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
  711. 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
  712. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
  713. audio_h_parents, 0xf0, 0xf4, 0xf8,
  714. 8, 2, 15, 0x008, 22),
  715. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
  716. 0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
  717. };
  718. static const char * const i2s0_m_ck_parents[] = {
  719. "aud_1_sel",
  720. "aud_2_sel"
  721. };
  722. static const char * const i2s1_m_ck_parents[] = {
  723. "aud_1_sel",
  724. "aud_2_sel"
  725. };
  726. static const char * const i2s2_m_ck_parents[] = {
  727. "aud_1_sel",
  728. "aud_2_sel"
  729. };
  730. static const char * const i2s3_m_ck_parents[] = {
  731. "aud_1_sel",
  732. "aud_2_sel"
  733. };
  734. static const char * const i2s4_m_ck_parents[] = {
  735. "aud_1_sel",
  736. "aud_2_sel"
  737. };
  738. static const char * const i2s5_m_ck_parents[] = {
  739. "aud_1_sel",
  740. "aud_2_sel"
  741. };
  742. static const struct mtk_composite top_aud_muxes[] = {
  743. MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
  744. 0x320, 8, 1),
  745. MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
  746. 0x320, 9, 1),
  747. MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
  748. 0x320, 10, 1),
  749. MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
  750. 0x320, 11, 1),
  751. MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
  752. 0x320, 12, 1),
  753. MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
  754. 0x328, 20, 1),
  755. };
  756. static struct mtk_composite top_aud_divs[] = {
  757. DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
  758. 0x320, 2, 0x324, 8, 0),
  759. DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
  760. 0x320, 3, 0x324, 8, 8),
  761. DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
  762. 0x320, 4, 0x324, 8, 16),
  763. DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
  764. 0x320, 5, 0x324, 8, 24),
  765. DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
  766. 0x320, 6, 0x328, 8, 0),
  767. DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
  768. 0x320, 7, 0x328, 8, 8),
  769. DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
  770. 0x328, 16, 0x328, 4, 28),
  771. };
  772. static const struct mtk_gate_regs infra0_cg_regs = {
  773. .set_ofs = 0x80,
  774. .clr_ofs = 0x84,
  775. .sta_ofs = 0x90,
  776. };
  777. static const struct mtk_gate_regs infra1_cg_regs = {
  778. .set_ofs = 0x88,
  779. .clr_ofs = 0x8c,
  780. .sta_ofs = 0x94,
  781. };
  782. static const struct mtk_gate_regs infra2_cg_regs = {
  783. .set_ofs = 0xa4,
  784. .clr_ofs = 0xa8,
  785. .sta_ofs = 0xac,
  786. };
  787. static const struct mtk_gate_regs infra3_cg_regs = {
  788. .set_ofs = 0xc0,
  789. .clr_ofs = 0xc4,
  790. .sta_ofs = 0xc8,
  791. };
  792. #define GATE_INFRA0(_id, _name, _parent, _shift) \
  793. GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
  794. &mtk_clk_gate_ops_setclr)
  795. #define GATE_INFRA1(_id, _name, _parent, _shift) \
  796. GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
  797. &mtk_clk_gate_ops_setclr)
  798. #define GATE_INFRA2(_id, _name, _parent, _shift) \
  799. GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
  800. &mtk_clk_gate_ops_setclr)
  801. #define GATE_INFRA3(_id, _name, _parent, _shift) \
  802. GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
  803. &mtk_clk_gate_ops_setclr)
  804. static const struct mtk_gate infra_clks[] = {
  805. /* INFRA0 */
  806. GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
  807. "axi_sel", 0),
  808. GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
  809. "axi_sel", 1),
  810. GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
  811. "axi_sel", 2),
  812. GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
  813. "axi_sel", 3),
  814. GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
  815. "axi_sel", 4),
  816. GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
  817. "f_f26m_ck", 5),
  818. GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
  819. "axi_sel", 6),
  820. GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
  821. "axi_sel", 8),
  822. GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
  823. "axi_sel", 9),
  824. GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
  825. "axi_sel", 10),
  826. GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
  827. "i2c_sel", 11),
  828. GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
  829. "i2c_sel", 12),
  830. GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
  831. "i2c_sel", 13),
  832. GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
  833. "i2c_sel", 14),
  834. GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
  835. "pwm_sel", 15),
  836. GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
  837. "pwm_sel", 16),
  838. GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
  839. "pwm_sel", 17),
  840. GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
  841. "pwm_sel", 18),
  842. GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
  843. "pwm_sel", 19),
  844. GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
  845. "pwm_sel", 21),
  846. GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
  847. "uart_sel", 22),
  848. GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
  849. "uart_sel", 23),
  850. GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
  851. "uart_sel", 24),
  852. GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
  853. "uart_sel", 25),
  854. GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
  855. "axi_sel", 27),
  856. GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
  857. "axi_sel", 28),
  858. GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
  859. "axi_sel", 31),
  860. /* INFRA1 */
  861. GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
  862. "spi_sel", 1),
  863. GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
  864. "msdc50_hclk_sel", 2),
  865. GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
  866. "axi_sel", 4),
  867. GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
  868. "axi_sel", 5),
  869. GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
  870. "msdc50_0_sel", 6),
  871. GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
  872. "f_f26m_ck", 7),
  873. GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
  874. "axi_sel", 8),
  875. GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
  876. "axi_sel", 9),
  877. GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
  878. "f_f26m_ck", 10),
  879. GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
  880. "axi_sel", 11),
  881. GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
  882. "axi_sel", 12),
  883. GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
  884. "axi_sel", 13),
  885. GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
  886. "f_f26m_ck", 14),
  887. GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
  888. "msdc30_1_sel", 16),
  889. GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
  890. "msdc30_2_sel", 17),
  891. GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
  892. "axi_sel", 18),
  893. GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
  894. "axi_sel", 19),
  895. GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
  896. "axi_sel", 20),
  897. GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
  898. "axi_sel", 23),
  899. GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
  900. "axi_sel", 24),
  901. GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
  902. "axi_sel", 25),
  903. GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
  904. "axi_sel", 26),
  905. GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
  906. "dxcc_sel", 27),
  907. GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
  908. "dxcc_sel", 28),
  909. GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
  910. "axi_sel", 30),
  911. GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
  912. "f_f26m_ck", 31),
  913. /* INFRA2 */
  914. GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
  915. "f_f26m_ck", 0),
  916. GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
  917. "usb_top_sel", 1),
  918. GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
  919. "axi_sel", 2),
  920. GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
  921. "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
  922. GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
  923. "spi_sel", 6),
  924. GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
  925. "i2c_sel", 7),
  926. GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
  927. "f_f26m_ck", 8),
  928. GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
  929. "spi_sel", 9),
  930. GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
  931. "spi_sel", 10),
  932. GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
  933. "fufs_sel", 11),
  934. GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
  935. "fufs_sel", 12),
  936. GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
  937. "fufs_sel", 13),
  938. GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
  939. "axi_sel", 14),
  940. GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
  941. "axi_sel", 16),
  942. GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
  943. "axi_sel", 17),
  944. GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
  945. "i2c_sel", 18),
  946. GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
  947. "i2c_sel", 19),
  948. GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
  949. "i2c_sel", 20),
  950. GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
  951. "i2c_sel", 21),
  952. GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
  953. "i2c_sel", 22),
  954. GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
  955. "i2c_sel", 23),
  956. GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
  957. "i2c_sel", 24),
  958. GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
  959. "spi_sel", 25),
  960. GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
  961. "spi_sel", 26),
  962. GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
  963. "axi_sel", 27),
  964. GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
  965. "fufs_sel", 28),
  966. GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
  967. "faes_ufsfde_sel", 29),
  968. GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
  969. "fufs_sel", 30),
  970. GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
  971. "ssusb_top_xhci_sel", 31),
  972. /* INFRA3 */
  973. GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
  974. "msdc50_0_sel", 0),
  975. GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
  976. "msdc50_0_sel", 1),
  977. GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
  978. "msdc50_0_sel", 2),
  979. GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
  980. "f_f26m_ck", 3),
  981. GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
  982. "f_f26m_ck", 4),
  983. GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
  984. "axi_sel", 5),
  985. GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
  986. "i2c_sel", 6),
  987. GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
  988. "msdc50_hclk_sel", 7),
  989. GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
  990. "msdc50_hclk_sel", 8),
  991. GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
  992. "axi_sel", 16),
  993. GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
  994. "axi_sel", 17),
  995. GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
  996. "axi_sel", 18),
  997. GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
  998. "axi_sel", 19),
  999. GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
  1000. "f_f26m_ck", 20),
  1001. GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
  1002. "axi_sel", 21),
  1003. GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
  1004. "i2c_sel", 22),
  1005. GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
  1006. "i2c_sel", 23),
  1007. GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
  1008. "msdc50_0_sel", 24),
  1009. GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
  1010. "dpmaif_sel", 26),
  1011. GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
  1012. "adsp_sel", 27),
  1013. GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
  1014. "axi_sel", 28),
  1015. GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
  1016. "axi_sel", 29),
  1017. GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
  1018. "spi_sel", 30),
  1019. GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
  1020. "spi_sel", 31),
  1021. };
  1022. static const struct mtk_gate_regs apmixed_cg_regs = {
  1023. .set_ofs = 0x20,
  1024. .clr_ofs = 0x20,
  1025. .sta_ofs = 0x20,
  1026. };
  1027. #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
  1028. GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
  1029. _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
  1030. #define GATE_APMIXED(_id, _name, _parent, _shift) \
  1031. GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
  1032. /*
  1033. * CRITICAL CLOCK:
  1034. * apmixed_appll26m is the toppest clock gate of all PLLs.
  1035. */
  1036. static const struct mtk_gate apmixed_clks[] = {
  1037. GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
  1038. "f_f26m_ck", 4),
  1039. GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
  1040. "f_f26m_ck", 5, CLK_IS_CRITICAL),
  1041. GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
  1042. "f_f26m_ck", 6),
  1043. GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
  1044. "f_f26m_ck", 7),
  1045. GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
  1046. "f_f26m_ck", 8),
  1047. GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
  1048. "f_f26m_ck", 9),
  1049. GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
  1050. "f_f26m_ck", 11),
  1051. GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
  1052. "f_f26m_ck", 13),
  1053. GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
  1054. "f_f26m_ck", 14),
  1055. GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
  1056. "f_f26m_ck", 16),
  1057. GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
  1058. "f_f26m_ck", 17),
  1059. };
  1060. #define MT6779_PLL_FMAX (3800UL * MHZ)
  1061. #define MT6779_PLL_FMIN (1500UL * MHZ)
  1062. #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  1063. _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
  1064. _pd_shift, _tuner_reg, _tuner_en_reg, \
  1065. _tuner_en_bit, _pcw_reg, _pcw_shift, \
  1066. _pcw_chg_reg, _div_table) { \
  1067. .id = _id, \
  1068. .name = _name, \
  1069. .reg = _reg, \
  1070. .pwr_reg = _pwr_reg, \
  1071. .en_mask = _en_mask, \
  1072. .flags = _flags, \
  1073. .rst_bar_mask = _rst_bar_mask, \
  1074. .fmax = MT6779_PLL_FMAX, \
  1075. .fmin = MT6779_PLL_FMIN, \
  1076. .pcwbits = _pcwbits, \
  1077. .pcwibits = _pcwibits, \
  1078. .pd_reg = _pd_reg, \
  1079. .pd_shift = _pd_shift, \
  1080. .tuner_reg = _tuner_reg, \
  1081. .tuner_en_reg = _tuner_en_reg, \
  1082. .tuner_en_bit = _tuner_en_bit, \
  1083. .pcw_reg = _pcw_reg, \
  1084. .pcw_shift = _pcw_shift, \
  1085. .pcw_chg_reg = _pcw_chg_reg, \
  1086. .div_table = _div_table, \
  1087. }
  1088. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  1089. _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
  1090. _pd_shift, _tuner_reg, _tuner_en_reg, \
  1091. _tuner_en_bit, _pcw_reg, _pcw_shift, \
  1092. _pcw_chg_reg) \
  1093. PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  1094. _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
  1095. _pd_shift, _tuner_reg, _tuner_en_reg, \
  1096. _tuner_en_bit, _pcw_reg, _pcw_shift, \
  1097. _pcw_chg_reg, NULL)
  1098. static const struct mtk_pll_data plls[] = {
  1099. PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
  1100. PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
  1101. PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
  1102. PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
  1103. PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
  1104. PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
  1105. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
  1106. (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
  1107. 0x0234, 0, 0),
  1108. PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
  1109. (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
  1110. 0, 0, 0, 0x0244, 0, 0),
  1111. PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
  1112. 0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
  1113. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
  1114. 0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
  1115. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
  1116. 0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
  1117. PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
  1118. (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
  1119. 0, 0, 0, 0x02b4, 0, 0),
  1120. PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
  1121. (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
  1122. 0, 0, 0, 0x0284, 0, 0),
  1123. PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
  1124. 0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
  1125. PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
  1126. 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
  1127. };
  1128. static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
  1129. {
  1130. struct clk_onecell_data *clk_data;
  1131. struct device_node *node = pdev->dev.of_node;
  1132. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
  1133. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  1134. mtk_clk_register_gates(node, apmixed_clks,
  1135. ARRAY_SIZE(apmixed_clks), clk_data);
  1136. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1137. }
  1138. static int clk_mt6779_top_probe(struct platform_device *pdev)
  1139. {
  1140. void __iomem *base;
  1141. struct clk_onecell_data *clk_data;
  1142. struct device_node *node = pdev->dev.of_node;
  1143. base = devm_platform_ioremap_resource(pdev, 0);
  1144. if (IS_ERR(base))
  1145. return PTR_ERR(base);
  1146. clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
  1147. mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  1148. clk_data);
  1149. mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
  1150. mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
  1151. node, &mt6779_clk_lock, clk_data);
  1152. mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
  1153. base, &mt6779_clk_lock, clk_data);
  1154. mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
  1155. base, &mt6779_clk_lock, clk_data);
  1156. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1157. }
  1158. static int clk_mt6779_infra_probe(struct platform_device *pdev)
  1159. {
  1160. struct clk_onecell_data *clk_data;
  1161. struct device_node *node = pdev->dev.of_node;
  1162. clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  1163. mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  1164. clk_data);
  1165. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1166. }
  1167. static const struct of_device_id of_match_clk_mt6779[] = {
  1168. {
  1169. .compatible = "mediatek,mt6779-apmixed",
  1170. .data = clk_mt6779_apmixed_probe,
  1171. }, {
  1172. .compatible = "mediatek,mt6779-topckgen",
  1173. .data = clk_mt6779_top_probe,
  1174. }, {
  1175. .compatible = "mediatek,mt6779-infracfg_ao",
  1176. .data = clk_mt6779_infra_probe,
  1177. }, {
  1178. /* sentinel */
  1179. }
  1180. };
  1181. static int clk_mt6779_probe(struct platform_device *pdev)
  1182. {
  1183. int (*clk_probe)(struct platform_device *pdev);
  1184. int r;
  1185. clk_probe = of_device_get_match_data(&pdev->dev);
  1186. if (!clk_probe)
  1187. return -EINVAL;
  1188. r = clk_probe(pdev);
  1189. if (r)
  1190. dev_err(&pdev->dev,
  1191. "could not register clock provider: %s: %d\n",
  1192. pdev->name, r);
  1193. return r;
  1194. }
  1195. static struct platform_driver clk_mt6779_drv = {
  1196. .probe = clk_mt6779_probe,
  1197. .driver = {
  1198. .name = "clk-mt6779",
  1199. .of_match_table = of_match_clk_mt6779,
  1200. },
  1201. };
  1202. static int __init clk_mt6779_init(void)
  1203. {
  1204. return platform_driver_register(&clk_mt6779_drv);
  1205. }
  1206. arch_initcall(clk_mt6779_init);