clk-mt6779-mm.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. * Author: Wendell Lin <wendell.lin@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include <dt-bindings/clock/mt6779-clk.h>
  9. #include "clk-mtk.h"
  10. #include "clk-gate.h"
  11. static const struct mtk_gate_regs mm0_cg_regs = {
  12. .set_ofs = 0x0104,
  13. .clr_ofs = 0x0108,
  14. .sta_ofs = 0x0100,
  15. };
  16. static const struct mtk_gate_regs mm1_cg_regs = {
  17. .set_ofs = 0x0114,
  18. .clr_ofs = 0x0118,
  19. .sta_ofs = 0x0110,
  20. };
  21. #define GATE_MM0(_id, _name, _parent, _shift) \
  22. GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
  23. &mtk_clk_gate_ops_setclr)
  24. #define GATE_MM1(_id, _name, _parent, _shift) \
  25. GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
  26. &mtk_clk_gate_ops_setclr)
  27. static const struct mtk_gate mm_clks[] = {
  28. /* MM0 */
  29. GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
  30. GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
  31. GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
  32. GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
  33. GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
  34. GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
  35. GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
  36. GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
  37. GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
  38. GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
  39. GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
  40. GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
  41. GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
  42. GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
  43. GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
  44. GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
  45. GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
  46. GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
  47. GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
  48. GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
  49. GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
  50. GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
  51. GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
  52. GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
  53. GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
  54. GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
  55. GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
  56. GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
  57. GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
  58. GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
  59. GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
  60. GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
  61. /* MM1 */
  62. GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
  63. GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
  64. GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
  65. GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
  66. GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
  67. GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
  68. GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
  69. GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
  70. GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
  71. GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
  72. GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
  73. GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
  74. GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
  75. GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
  76. GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
  77. GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
  78. GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
  79. };
  80. static int clk_mt6779_mm_probe(struct platform_device *pdev)
  81. {
  82. struct device *dev = &pdev->dev;
  83. struct device_node *node = dev->parent->of_node;
  84. struct clk_onecell_data *clk_data;
  85. clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
  86. mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
  87. clk_data);
  88. return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  89. }
  90. static struct platform_driver clk_mt6779_mm_drv = {
  91. .probe = clk_mt6779_mm_probe,
  92. .driver = {
  93. .name = "clk-mt6779-mm",
  94. },
  95. };
  96. builtin_platform_driver(clk_mt6779_mm_drv);