clk-mt6765.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 MediaTek Inc.
  4. * Author: Owen Chen <owen.chen@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/slab.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include "clk-mtk.h"
  14. #include "clk-gate.h"
  15. #include "clk-mux.h"
  16. #include <dt-bindings/clock/mt6765-clk.h>
  17. /*fmeter div select 4*/
  18. #define _DIV4_ 1
  19. static DEFINE_SPINLOCK(mt6765_clk_lock);
  20. /* Total 12 subsys */
  21. static void __iomem *cksys_base;
  22. static void __iomem *apmixed_base;
  23. /* CKSYS */
  24. #define CLK_SCP_CFG_0 (cksys_base + 0x200)
  25. #define CLK_SCP_CFG_1 (cksys_base + 0x204)
  26. /* CG */
  27. #define AP_PLL_CON3 (apmixed_base + 0x0C)
  28. #define PLLON_CON0 (apmixed_base + 0x44)
  29. #define PLLON_CON1 (apmixed_base + 0x48)
  30. /* clk cfg update */
  31. #define CLK_CFG_0 0x40
  32. #define CLK_CFG_0_SET 0x44
  33. #define CLK_CFG_0_CLR 0x48
  34. #define CLK_CFG_1 0x50
  35. #define CLK_CFG_1_SET 0x54
  36. #define CLK_CFG_1_CLR 0x58
  37. #define CLK_CFG_2 0x60
  38. #define CLK_CFG_2_SET 0x64
  39. #define CLK_CFG_2_CLR 0x68
  40. #define CLK_CFG_3 0x70
  41. #define CLK_CFG_3_SET 0x74
  42. #define CLK_CFG_3_CLR 0x78
  43. #define CLK_CFG_4 0x80
  44. #define CLK_CFG_4_SET 0x84
  45. #define CLK_CFG_4_CLR 0x88
  46. #define CLK_CFG_5 0x90
  47. #define CLK_CFG_5_SET 0x94
  48. #define CLK_CFG_5_CLR 0x98
  49. #define CLK_CFG_6 0xa0
  50. #define CLK_CFG_6_SET 0xa4
  51. #define CLK_CFG_6_CLR 0xa8
  52. #define CLK_CFG_7 0xb0
  53. #define CLK_CFG_7_SET 0xb4
  54. #define CLK_CFG_7_CLR 0xb8
  55. #define CLK_CFG_8 0xc0
  56. #define CLK_CFG_8_SET 0xc4
  57. #define CLK_CFG_8_CLR 0xc8
  58. #define CLK_CFG_9 0xd0
  59. #define CLK_CFG_9_SET 0xd4
  60. #define CLK_CFG_9_CLR 0xd8
  61. #define CLK_CFG_10 0xe0
  62. #define CLK_CFG_10_SET 0xe4
  63. #define CLK_CFG_10_CLR 0xe8
  64. #define CLK_CFG_UPDATE 0x004
  65. static const struct mtk_fixed_clk fixed_clks[] = {
  66. FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768),
  67. FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000),
  68. FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000),
  69. };
  70. static const struct mtk_fixed_factor top_divs[] = {
  71. FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
  72. FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  73. FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  74. FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  75. FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  76. FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  77. FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  78. FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  79. FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  80. FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  81. FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  82. FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  83. FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  84. FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  85. FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  86. FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  87. FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
  88. FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13),
  89. FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
  90. FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
  91. FACTOR(CLK_TOP_USB20_192M_D16,
  92. "usb20_192m_d16", "usb20_192m_ck", 1, 16),
  93. FACTOR(CLK_TOP_USB20_192M_D32,
  94. "usb20_192m_d32", "usb20_192m_ck", 1, 32),
  95. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  96. FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
  97. FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
  98. FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  99. FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
  100. FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
  101. FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
  102. FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
  103. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  104. FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
  105. FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
  106. FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
  107. FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2),
  108. FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1),
  109. FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2),
  110. FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4),
  111. FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
  112. FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
  113. FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
  114. FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
  115. FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
  116. FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
  117. FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
  118. FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1),
  119. FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2),
  120. FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4),
  121. FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8),
  122. FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16),
  123. FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32),
  124. FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1),
  125. FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1),
  126. FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1),
  127. FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1),
  128. FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1),
  129. FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
  130. FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1),
  131. FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
  132. FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1),
  133. FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1),
  134. FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),
  135. FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1),
  136. FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1),
  137. FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1),
  138. FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1),
  139. FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1),
  140. FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1),
  141. FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1),
  142. FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1),
  143. FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1),
  144. FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1),
  145. FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1),
  146. FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1),
  147. FACTOR(CLK_TOP_DA_USB20_48M_DIV,
  148. "usb20_48m_div", "usb20_192m_d4", 1, 1),
  149. FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1),
  150. };
  151. static const char * const axi_parents[] = {
  152. "clk26m",
  153. "syspll_d7",
  154. "syspll1_d4",
  155. "syspll3_d2"
  156. };
  157. static const char * const mem_parents[] = {
  158. "clk26m",
  159. "dmpll_ck",
  160. "apll1_ck"
  161. };
  162. static const char * const mm_parents[] = {
  163. "clk26m",
  164. "mmpll_ck",
  165. "syspll1_d2",
  166. "syspll_d5",
  167. "syspll1_d4",
  168. "univpll_d5",
  169. "univpll1_d2",
  170. "mmpll_d2"
  171. };
  172. static const char * const scp_parents[] = {
  173. "clk26m",
  174. "syspll4_d2",
  175. "univpll2_d2",
  176. "syspll1_d2",
  177. "univpll1_d2",
  178. "syspll_d3",
  179. "univpll_d3"
  180. };
  181. static const char * const mfg_parents[] = {
  182. "clk26m",
  183. "mfgpll_ck",
  184. "syspll_d3",
  185. "univpll_d3"
  186. };
  187. static const char * const atb_parents[] = {
  188. "clk26m",
  189. "syspll1_d4",
  190. "syspll1_d2"
  191. };
  192. static const char * const camtg_parents[] = {
  193. "clk26m",
  194. "usb20_192m_d8",
  195. "univpll2_d8",
  196. "usb20_192m_d4",
  197. "univpll2_d32",
  198. "usb20_192m_d16",
  199. "usb20_192m_d32"
  200. };
  201. static const char * const uart_parents[] = {
  202. "clk26m",
  203. "univpll2_d8"
  204. };
  205. static const char * const spi_parents[] = {
  206. "clk26m",
  207. "syspll3_d2",
  208. "syspll4_d2",
  209. "syspll2_d4"
  210. };
  211. static const char * const msdc5hclk_parents[] = {
  212. "clk26m",
  213. "syspll1_d2",
  214. "univpll1_d4",
  215. "syspll2_d2"
  216. };
  217. static const char * const msdc50_0_parents[] = {
  218. "clk26m",
  219. "msdcpll_ck",
  220. "syspll2_d2",
  221. "syspll4_d2",
  222. "univpll1_d2",
  223. "syspll1_d2",
  224. "univpll_d5",
  225. "univpll1_d4"
  226. };
  227. static const char * const msdc30_1_parents[] = {
  228. "clk26m",
  229. "msdcpll_d2",
  230. "univpll2_d2",
  231. "syspll2_d2",
  232. "syspll1_d4",
  233. "univpll1_d4",
  234. "usb20_192m_d4",
  235. "syspll2_d4"
  236. };
  237. static const char * const audio_parents[] = {
  238. "clk26m",
  239. "syspll3_d4",
  240. "syspll4_d4",
  241. "syspll1_d16"
  242. };
  243. static const char * const aud_intbus_parents[] = {
  244. "clk26m",
  245. "syspll1_d4",
  246. "syspll4_d2"
  247. };
  248. static const char * const aud_1_parents[] = {
  249. "clk26m",
  250. "apll1_ck"
  251. };
  252. static const char * const aud_engen1_parents[] = {
  253. "clk26m",
  254. "apll1_d2",
  255. "apll1_d4",
  256. "apll1_d8"
  257. };
  258. static const char * const disp_pwm_parents[] = {
  259. "clk26m",
  260. "univpll2_d4",
  261. "ulposc1_d2",
  262. "ulposc1_d8"
  263. };
  264. static const char * const sspm_parents[] = {
  265. "clk26m",
  266. "syspll1_d2",
  267. "syspll_d3"
  268. };
  269. static const char * const dxcc_parents[] = {
  270. "clk26m",
  271. "syspll1_d2",
  272. "syspll1_d4",
  273. "syspll1_d8"
  274. };
  275. static const char * const usb_top_parents[] = {
  276. "clk26m",
  277. "univpll3_d4"
  278. };
  279. static const char * const spm_parents[] = {
  280. "clk26m",
  281. "syspll1_d8"
  282. };
  283. static const char * const i2c_parents[] = {
  284. "clk26m",
  285. "univpll3_d4",
  286. "univpll3_d2",
  287. "syspll1_d8",
  288. "syspll2_d8"
  289. };
  290. static const char * const pwm_parents[] = {
  291. "clk26m",
  292. "univpll3_d4",
  293. "syspll1_d8"
  294. };
  295. static const char * const seninf_parents[] = {
  296. "clk26m",
  297. "univpll1_d4",
  298. "univpll1_d2",
  299. "univpll2_d2"
  300. };
  301. static const char * const aes_fde_parents[] = {
  302. "clk26m",
  303. "msdcpll_ck",
  304. "univpll_d3",
  305. "univpll2_d2",
  306. "univpll1_d2",
  307. "syspll1_d2"
  308. };
  309. static const char * const ulposc_parents[] = {
  310. "clk26m",
  311. "ulposc1_d4",
  312. "ulposc1_d8",
  313. "ulposc1_d16",
  314. "ulposc1_d32"
  315. };
  316. static const char * const camtm_parents[] = {
  317. "clk26m",
  318. "univpll1_d4",
  319. "univpll1_d2",
  320. "univpll2_d2"
  321. };
  322. #define INVALID_UPDATE_REG 0xFFFFFFFF
  323. #define INVALID_UPDATE_SHIFT -1
  324. #define INVALID_MUX_GATE -1
  325. static const struct mtk_mux top_muxes[] = {
  326. /* CLK_CFG_0 */
  327. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
  328. CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
  329. 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
  330. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
  331. CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
  332. 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
  333. MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
  334. CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
  335. CLK_CFG_UPDATE, 2),
  336. MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
  337. CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
  338. CLK_CFG_UPDATE, 3),
  339. /* CLK_CFG_1 */
  340. MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
  341. CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
  342. CLK_CFG_UPDATE, 4),
  343. MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
  344. CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
  345. CLK_CFG_UPDATE, 5),
  346. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
  347. camtg_parents, CLK_CFG_1, CLK_CFG_1_SET,
  348. CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
  349. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
  350. CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,
  351. 24, 3, 31, CLK_CFG_UPDATE, 7),
  352. /* CLK_CFG_2 */
  353. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
  354. camtg_parents, CLK_CFG_2, CLK_CFG_2_SET,
  355. CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8),
  356. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
  357. CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR,
  358. 8, 3, 15, CLK_CFG_UPDATE, 9),
  359. MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
  360. CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23,
  361. CLK_CFG_UPDATE, 10),
  362. MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
  363. CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
  364. CLK_CFG_UPDATE, 11),
  365. /* CLK_CFG_3 */
  366. MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
  367. msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
  368. CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
  369. MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
  370. msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
  371. CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
  372. MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
  373. msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
  374. CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
  375. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
  376. CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
  377. 24, 2, 31, CLK_CFG_UPDATE, 15),
  378. /* CLK_CFG_4 */
  379. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
  380. aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET,
  381. CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16),
  382. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
  383. CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR,
  384. 8, 1, 15, CLK_CFG_UPDATE, 17),
  385. MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
  386. aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET,
  387. CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18),
  388. MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
  389. disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET,
  390. CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19),
  391. /* CLK_CFG_5 */
  392. MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents,
  393. CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7,
  394. CLK_CFG_UPDATE, 20),
  395. MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
  396. CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15,
  397. CLK_CFG_UPDATE, 21),
  398. MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
  399. usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET,
  400. CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22),
  401. MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5,
  402. CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31,
  403. CLK_CFG_UPDATE, 23),
  404. /* CLK_CFG_6 */
  405. MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6,
  406. CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE,
  407. 24),
  408. MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
  409. CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE,
  410. 25),
  411. MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,
  412. CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23,
  413. CLK_CFG_UPDATE, 26),
  414. MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
  415. aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET,
  416. CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27),
  417. /* CLK_CFG_7 */
  418. MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
  419. ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
  420. CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
  421. CLK_IS_CRITICAL),
  422. MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
  423. CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
  424. CLK_CFG_UPDATE, 29),
  425. };
  426. static const struct mtk_gate_regs top0_cg_regs = {
  427. .set_ofs = 0x0,
  428. .clr_ofs = 0x0,
  429. .sta_ofs = 0x0,
  430. };
  431. static const struct mtk_gate_regs top1_cg_regs = {
  432. .set_ofs = 0x104,
  433. .clr_ofs = 0x104,
  434. .sta_ofs = 0x104,
  435. };
  436. static const struct mtk_gate_regs top2_cg_regs = {
  437. .set_ofs = 0x320,
  438. .clr_ofs = 0x320,
  439. .sta_ofs = 0x320,
  440. };
  441. #define GATE_TOP0(_id, _name, _parent, _shift) { \
  442. .id = _id, \
  443. .name = _name, \
  444. .parent_name = _parent, \
  445. .regs = &top0_cg_regs, \
  446. .shift = _shift, \
  447. .ops = &mtk_clk_gate_ops_no_setclr, \
  448. }
  449. #define GATE_TOP1(_id, _name, _parent, _shift) { \
  450. .id = _id, \
  451. .name = _name, \
  452. .parent_name = _parent, \
  453. .regs = &top1_cg_regs, \
  454. .shift = _shift, \
  455. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  456. }
  457. #define GATE_TOP2(_id, _name, _parent, _shift) { \
  458. .id = _id, \
  459. .name = _name, \
  460. .parent_name = _parent, \
  461. .regs = &top2_cg_regs, \
  462. .shift = _shift, \
  463. .ops = &mtk_clk_gate_ops_no_setclr, \
  464. }
  465. static const struct mtk_gate top_clks[] = {
  466. /* TOP0 */
  467. GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8),
  468. GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9),
  469. GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10),
  470. GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11),
  471. /* TOP1 */
  472. GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN,
  473. "arm_div_pll0_en", "arm_div_pll0", 3),
  474. GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
  475. "arm_div_pll1_en", "arm_div_pll1", 4),
  476. GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
  477. "arm_div_pll2_en", "arm_div_pll2", 5),
  478. GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6),
  479. GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8),
  480. GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9),
  481. GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12),
  482. GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16),
  483. /* TOP2 */
  484. GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
  485. GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
  486. GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
  487. GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
  488. };
  489. static const struct mtk_gate_regs ifr2_cg_regs = {
  490. .set_ofs = 0x80,
  491. .clr_ofs = 0x84,
  492. .sta_ofs = 0x90,
  493. };
  494. static const struct mtk_gate_regs ifr3_cg_regs = {
  495. .set_ofs = 0x88,
  496. .clr_ofs = 0x8c,
  497. .sta_ofs = 0x94,
  498. };
  499. static const struct mtk_gate_regs ifr4_cg_regs = {
  500. .set_ofs = 0xa4,
  501. .clr_ofs = 0xa8,
  502. .sta_ofs = 0xac,
  503. };
  504. static const struct mtk_gate_regs ifr5_cg_regs = {
  505. .set_ofs = 0xc0,
  506. .clr_ofs = 0xc4,
  507. .sta_ofs = 0xc8,
  508. };
  509. #define GATE_IFR2(_id, _name, _parent, _shift) { \
  510. .id = _id, \
  511. .name = _name, \
  512. .parent_name = _parent, \
  513. .regs = &ifr2_cg_regs, \
  514. .shift = _shift, \
  515. .ops = &mtk_clk_gate_ops_setclr, \
  516. }
  517. #define GATE_IFR3(_id, _name, _parent, _shift) { \
  518. .id = _id, \
  519. .name = _name, \
  520. .parent_name = _parent, \
  521. .regs = &ifr3_cg_regs, \
  522. .shift = _shift, \
  523. .ops = &mtk_clk_gate_ops_setclr, \
  524. }
  525. #define GATE_IFR4(_id, _name, _parent, _shift) { \
  526. .id = _id, \
  527. .name = _name, \
  528. .parent_name = _parent, \
  529. .regs = &ifr4_cg_regs, \
  530. .shift = _shift, \
  531. .ops = &mtk_clk_gate_ops_setclr, \
  532. }
  533. #define GATE_IFR5(_id, _name, _parent, _shift) { \
  534. .id = _id, \
  535. .name = _name, \
  536. .parent_name = _parent, \
  537. .regs = &ifr5_cg_regs, \
  538. .shift = _shift, \
  539. .ops = &mtk_clk_gate_ops_setclr, \
  540. }
  541. static const struct mtk_gate ifr_clks[] = {
  542. /* INFRA_TOPAXI */
  543. /* INFRA PERI */
  544. /* INFRA mode 0 */
  545. GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8),
  546. GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9),
  547. GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10),
  548. GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11),
  549. GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12),
  550. GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13),
  551. GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14),
  552. GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15),
  553. GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16),
  554. GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17),
  555. GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18),
  556. GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19),
  557. GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20),
  558. GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21),
  559. GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22),
  560. GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23),
  561. GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27),
  562. GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28),
  563. GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31),
  564. /* INFRA mode 1 */
  565. GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1),
  566. GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2),
  567. GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4),
  568. GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9),
  569. GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10),
  570. GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12),
  571. GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13),
  572. GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14),
  573. GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18),
  574. GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20),
  575. GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23),
  576. GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25),
  577. GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26),
  578. /* INFRA mode 2 */
  579. GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0),
  580. GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2),
  581. GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3),
  582. GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4),
  583. GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6),
  584. GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7),
  585. GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9),
  586. GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10),
  587. GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18),
  588. GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19),
  589. GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20),
  590. GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21),
  591. GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22),
  592. GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23),
  593. GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24),
  594. GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25),
  595. GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26),
  596. GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27),
  597. GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29),
  598. /* INFRA mode 3 */
  599. GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0),
  600. GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1),
  601. GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6),
  602. GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7),
  603. GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8),
  604. GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9),
  605. GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10),
  606. GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17),
  607. GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18),
  608. GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19),
  609. GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20),
  610. GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21),
  611. };
  612. /* additional CCF control for mipi26M race condition(disp/camera) */
  613. static const struct mtk_gate_regs apmixed_cg_regs = {
  614. .set_ofs = 0x14,
  615. .clr_ofs = 0x14,
  616. .sta_ofs = 0x14,
  617. };
  618. #define GATE_APMIXED(_id, _name, _parent, _shift) { \
  619. .id = _id, \
  620. .name = _name, \
  621. .parent_name = _parent, \
  622. .regs = &apmixed_cg_regs, \
  623. .shift = _shift, \
  624. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  625. }
  626. static const struct mtk_gate apmixed_clks[] = {
  627. /* AUDIO0 */
  628. GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck",
  629. 4),
  630. GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck",
  631. 5),
  632. GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck",
  633. 6),
  634. GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck",
  635. 7),
  636. GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck",
  637. 8),
  638. GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck",
  639. 9),
  640. GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck",
  641. 11),
  642. GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck",
  643. 13),
  644. GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
  645. "f_f26m_ck", 14),
  646. GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck",
  647. 16),
  648. };
  649. #define MT6765_PLL_FMAX (3800UL * MHZ)
  650. #define MT6765_PLL_FMIN (1500UL * MHZ)
  651. #define CON0_MT6765_RST_BAR BIT(23)
  652. #define PLL_INFO_NULL (0xFF)
  653. #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  654. _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\
  655. _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\
  656. .id = _id, \
  657. .name = _name, \
  658. .reg = _reg, \
  659. .pwr_reg = _pwr_reg, \
  660. .en_mask = _en_mask, \
  661. .flags = _flags, \
  662. .rst_bar_mask = CON0_MT6765_RST_BAR, \
  663. .fmax = MT6765_PLL_FMAX, \
  664. .fmin = MT6765_PLL_FMIN, \
  665. .pcwbits = _pcwbits, \
  666. .pcwibits = _pcwibits, \
  667. .pd_reg = _pd_reg, \
  668. .pd_shift = _pd_shift, \
  669. .tuner_reg = _tuner_reg, \
  670. .tuner_en_reg = _tuner_en_reg, \
  671. .tuner_en_bit = _tuner_en_bit, \
  672. .pcw_reg = _pcw_reg, \
  673. .pcw_shift = _pcw_shift, \
  674. .div_table = _div_table, \
  675. }
  676. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  677. _pcwibits, _pd_reg, _pd_shift, _tuner_reg, \
  678. _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
  679. _pcw_shift) \
  680. PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  681. _pcwbits, _pcwibits, _pd_reg, _pd_shift, \
  682. _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
  683. _pcw_reg, _pcw_shift, NULL) \
  684. static const struct mtk_pll_data plls[] = {
  685. PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
  686. PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
  687. PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
  688. PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
  689. PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
  690. PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
  691. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
  692. (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
  693. 0),
  694. PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
  695. 0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
  696. PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
  697. 0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
  698. PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
  699. HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
  700. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
  701. 0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
  702. PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
  703. 0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
  704. PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
  705. PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
  706. };
  707. static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
  708. {
  709. struct clk_onecell_data *clk_data;
  710. int r;
  711. struct device_node *node = pdev->dev.of_node;
  712. void __iomem *base;
  713. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  714. base = devm_ioremap_resource(&pdev->dev, res);
  715. if (IS_ERR(base)) {
  716. pr_err("%s(): ioremap failed\n", __func__);
  717. return PTR_ERR(base);
  718. }
  719. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
  720. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  721. mtk_clk_register_gates(node, apmixed_clks,
  722. ARRAY_SIZE(apmixed_clks), clk_data);
  723. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  724. if (r)
  725. pr_err("%s(): could not register clock provider: %d\n",
  726. __func__, r);
  727. apmixed_base = base;
  728. /* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */
  729. writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3);
  730. writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0);
  731. writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1);
  732. return r;
  733. }
  734. static int clk_mt6765_top_probe(struct platform_device *pdev)
  735. {
  736. int r;
  737. struct device_node *node = pdev->dev.of_node;
  738. void __iomem *base;
  739. struct clk_onecell_data *clk_data;
  740. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  741. base = devm_ioremap_resource(&pdev->dev, res);
  742. if (IS_ERR(base)) {
  743. pr_err("%s(): ioremap failed\n", __func__);
  744. return PTR_ERR(base);
  745. }
  746. clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
  747. mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
  748. clk_data);
  749. mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
  750. clk_data);
  751. mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
  752. &mt6765_clk_lock, clk_data);
  753. mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  754. clk_data);
  755. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  756. if (r)
  757. pr_err("%s(): could not register clock provider: %d\n",
  758. __func__, r);
  759. cksys_base = base;
  760. /* [4]:no need */
  761. writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0);
  762. /*[1,2,3,8]: no need*/
  763. writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1);
  764. return r;
  765. }
  766. static int clk_mt6765_ifr_probe(struct platform_device *pdev)
  767. {
  768. struct clk_onecell_data *clk_data;
  769. int r;
  770. struct device_node *node = pdev->dev.of_node;
  771. void __iomem *base;
  772. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  773. base = devm_ioremap_resource(&pdev->dev, res);
  774. if (IS_ERR(base)) {
  775. pr_err("%s(): ioremap failed\n", __func__);
  776. return PTR_ERR(base);
  777. }
  778. clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
  779. mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
  780. clk_data);
  781. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  782. if (r)
  783. pr_err("%s(): could not register clock provider: %d\n",
  784. __func__, r);
  785. return r;
  786. }
  787. static const struct of_device_id of_match_clk_mt6765[] = {
  788. {
  789. .compatible = "mediatek,mt6765-apmixedsys",
  790. .data = clk_mt6765_apmixed_probe,
  791. }, {
  792. .compatible = "mediatek,mt6765-topckgen",
  793. .data = clk_mt6765_top_probe,
  794. }, {
  795. .compatible = "mediatek,mt6765-infracfg",
  796. .data = clk_mt6765_ifr_probe,
  797. }, {
  798. /* sentinel */
  799. }
  800. };
  801. static int clk_mt6765_probe(struct platform_device *pdev)
  802. {
  803. int (*clk_probe)(struct platform_device *d);
  804. int r;
  805. clk_probe = of_device_get_match_data(&pdev->dev);
  806. if (!clk_probe)
  807. return -EINVAL;
  808. r = clk_probe(pdev);
  809. if (r)
  810. dev_err(&pdev->dev,
  811. "could not register clock provider: %s: %d\n",
  812. pdev->name, r);
  813. return r;
  814. }
  815. static struct platform_driver clk_mt6765_drv = {
  816. .probe = clk_mt6765_probe,
  817. .driver = {
  818. .name = "clk-mt6765",
  819. .of_match_table = of_match_clk_mt6765,
  820. },
  821. };
  822. static int __init clk_mt6765_init(void)
  823. {
  824. return platform_driver_register(&clk_mt6765_drv);
  825. }
  826. arch_initcall(clk_mt6765_init);