clk-mt6765-mipi0a.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018 MediaTek Inc.
  4. * Author: Owen Chen <owen.chen@mediatek.com>
  5. */
  6. #include <linux/clk-provider.h>
  7. #include <linux/platform_device.h>
  8. #include "clk-mtk.h"
  9. #include "clk-gate.h"
  10. #include <dt-bindings/clock/mt6765-clk.h>
  11. static const struct mtk_gate_regs mipi0a_cg_regs = {
  12. .set_ofs = 0x80,
  13. .clr_ofs = 0x80,
  14. .sta_ofs = 0x80,
  15. };
  16. #define GATE_MIPI0A(_id, _name, _parent, _shift) { \
  17. .id = _id, \
  18. .name = _name, \
  19. .parent_name = _parent, \
  20. .regs = &mipi0a_cg_regs, \
  21. .shift = _shift, \
  22. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  23. }
  24. static const struct mtk_gate mipi0a_clks[] = {
  25. GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A,
  26. "mipi0a_csr_0a", "f_fseninf_ck", 1),
  27. };
  28. static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
  29. {
  30. struct clk_onecell_data *clk_data;
  31. int r;
  32. struct device_node *node = pdev->dev.of_node;
  33. clk_data = mtk_alloc_clk_data(CLK_MIPI0A_NR_CLK);
  34. mtk_clk_register_gates(node, mipi0a_clks,
  35. ARRAY_SIZE(mipi0a_clks), clk_data);
  36. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  37. if (r)
  38. pr_err("%s(): could not register clock provider: %d\n",
  39. __func__, r);
  40. return r;
  41. }
  42. static const struct of_device_id of_match_clk_mt6765_mipi0a[] = {
  43. { .compatible = "mediatek,mt6765-mipi0a", },
  44. {}
  45. };
  46. static struct platform_driver clk_mt6765_mipi0a_drv = {
  47. .probe = clk_mt6765_mipi0a_probe,
  48. .driver = {
  49. .name = "clk-mt6765-mipi0a",
  50. .of_match_table = of_match_clk_mt6765_mipi0a,
  51. },
  52. };
  53. builtin_platform_driver(clk_mt6765_mipi0a_drv);