clk-mt2712.c 37 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Weiyi Lu <weiyi.lu@mediatek.com>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/mfd/syscon.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/of_device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include "clk-mtk.h"
  15. #include "clk-gate.h"
  16. #include <dt-bindings/clock/mt2712-clk.h>
  17. static DEFINE_SPINLOCK(mt2712_clk_lock);
  18. static const struct mtk_fixed_clk top_fixed_clks[] = {
  19. FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
  20. FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
  21. FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
  22. FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
  23. FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
  24. FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
  25. FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
  26. FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
  27. FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
  28. FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
  29. FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
  30. FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
  31. };
  32. static const struct mtk_fixed_factor top_early_divs[] = {
  33. FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
  34. 1),
  35. FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
  36. 2),
  37. };
  38. static const struct mtk_fixed_factor top_divs[] = {
  39. FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
  40. 1),
  41. FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
  42. 2),
  43. FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
  44. 3),
  45. FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
  46. 1),
  47. FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
  48. 1),
  49. FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
  50. 2),
  51. FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
  52. 2),
  53. FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
  54. 4),
  55. FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
  56. 8),
  57. FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
  58. 16),
  59. FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
  60. 3),
  61. FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
  62. 2),
  63. FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
  64. 4),
  65. FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
  66. 5),
  67. FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
  68. 2),
  69. FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
  70. 4),
  71. FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
  72. 7),
  73. FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
  74. 2),
  75. FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
  76. 4),
  77. FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
  78. 1),
  79. FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
  80. 7),
  81. FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
  82. 26),
  83. FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
  84. 52),
  85. FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
  86. 104),
  87. FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
  88. 208),
  89. FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
  90. 2),
  91. FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
  92. 2),
  93. FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
  94. 4),
  95. FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
  96. 8),
  97. FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
  98. 3),
  99. FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
  100. 2),
  101. FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
  102. 4),
  103. FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
  104. 8),
  105. FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
  106. 5),
  107. FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
  108. 2),
  109. FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
  110. 4),
  111. FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
  112. 8),
  113. FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
  114. 1),
  115. FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
  116. 1),
  117. FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
  118. 1),
  119. FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
  120. 1),
  121. FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
  122. 1),
  123. FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
  124. 1),
  125. FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
  126. 1),
  127. FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
  128. 2),
  129. FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
  130. 4),
  131. FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
  132. 8),
  133. FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
  134. 16),
  135. FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
  136. 1),
  137. FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
  138. 2),
  139. FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
  140. 4),
  141. FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
  142. 8),
  143. FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
  144. 16),
  145. FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
  146. 1),
  147. FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
  148. 2),
  149. FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
  150. 4),
  151. FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
  152. 8),
  153. FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
  154. 1),
  155. FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
  156. 2),
  157. FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
  158. 4),
  159. FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
  160. 8),
  161. FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
  162. 1),
  163. FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
  164. 1),
  165. FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
  166. 1),
  167. FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
  168. 2),
  169. FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
  170. 1),
  171. FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
  172. 2),
  173. FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
  174. 1),
  175. FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
  176. 2),
  177. FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
  178. 1),
  179. FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
  180. 2),
  181. FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
  182. 1),
  183. FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
  184. 2),
  185. FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
  186. 4),
  187. FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
  188. 8),
  189. FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
  190. 1),
  191. FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
  192. 2),
  193. FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
  194. 4),
  195. FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
  196. 1),
  197. FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
  198. 2),
  199. FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
  200. 4),
  201. FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
  202. 1),
  203. FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
  204. 2),
  205. FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
  206. 4),
  207. FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
  208. 4),
  209. FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
  210. 3),
  211. FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
  212. 3),
  213. };
  214. static const char * const axi_parents[] = {
  215. "clk26m",
  216. "syspll1_d2",
  217. "syspll_d5",
  218. "syspll1_d4",
  219. "univpll_d5",
  220. "univpll2_d2",
  221. "msdcpll2_ck"
  222. };
  223. static const char * const mem_parents[] = {
  224. "clk26m",
  225. "dmpll_ck"
  226. };
  227. static const char * const mm_parents[] = {
  228. "clk26m",
  229. "vencpll_ck",
  230. "syspll_d3",
  231. "syspll1_d2",
  232. "syspll_d5",
  233. "syspll1_d4",
  234. "univpll1_d2",
  235. "univpll2_d2"
  236. };
  237. static const char * const pwm_parents[] = {
  238. "clk26m",
  239. "univpll2_d4",
  240. "univpll3_d2",
  241. "univpll1_d4"
  242. };
  243. static const char * const vdec_parents[] = {
  244. "clk26m",
  245. "vcodecpll_ck",
  246. "tvdpll_429m",
  247. "univpll_d3",
  248. "vencpll_ck",
  249. "syspll_d3",
  250. "univpll1_d2",
  251. "mmpll_d2",
  252. "syspll3_d2",
  253. "tvdpll_ck"
  254. };
  255. static const char * const venc_parents[] = {
  256. "clk26m",
  257. "univpll1_d2",
  258. "mmpll_d2",
  259. "tvdpll_d2",
  260. "syspll1_d2",
  261. "univpll_d5",
  262. "vcodecpll_d2",
  263. "univpll2_d2",
  264. "syspll3_d2"
  265. };
  266. static const char * const mfg_parents[] = {
  267. "clk26m",
  268. "mmpll_ck",
  269. "univpll_d3",
  270. "clk26m",
  271. "clk26m",
  272. "clk26m",
  273. "clk26m",
  274. "clk26m",
  275. "clk26m",
  276. "syspll_d3",
  277. "syspll1_d2",
  278. "syspll_d5",
  279. "univpll_d3",
  280. "univpll1_d2",
  281. "univpll_d5",
  282. "univpll2_d2"
  283. };
  284. static const char * const camtg_parents[] = {
  285. "clk26m",
  286. "univpll_d52",
  287. "univpll_d208",
  288. "univpll_d104",
  289. "clk26m_d2",
  290. "univpll_d26",
  291. "univpll2_d8",
  292. "syspll3_d4",
  293. "syspll3_d2",
  294. "univpll1_d4",
  295. "univpll2_d2"
  296. };
  297. static const char * const uart_parents[] = {
  298. "clk26m",
  299. "univpll2_d8"
  300. };
  301. static const char * const spi_parents[] = {
  302. "clk26m",
  303. "univpll2_d4",
  304. "univpll1_d4",
  305. "univpll2_d2",
  306. "univpll3_d2",
  307. "univpll1_d8"
  308. };
  309. static const char * const usb20_parents[] = {
  310. "clk26m",
  311. "univpll1_d8",
  312. "univpll3_d4"
  313. };
  314. static const char * const usb30_parents[] = {
  315. "clk26m",
  316. "univpll3_d2",
  317. "univpll3_d4",
  318. "univpll2_d4"
  319. };
  320. static const char * const msdc50_0_h_parents[] = {
  321. "clk26m",
  322. "syspll1_d2",
  323. "syspll2_d2",
  324. "syspll4_d2",
  325. "univpll_d5",
  326. "univpll1_d4"
  327. };
  328. static const char * const msdc50_0_parents[] = {
  329. "clk26m",
  330. "msdcpll_ck",
  331. "msdcpll_d2",
  332. "univpll1_d4",
  333. "syspll2_d2",
  334. "msdcpll_d4",
  335. "vencpll_d2",
  336. "univpll1_d2",
  337. "msdcpll2_ck",
  338. "msdcpll2_d2",
  339. "msdcpll2_d4"
  340. };
  341. static const char * const msdc30_1_parents[] = {
  342. "clk26m",
  343. "univpll2_d2",
  344. "msdcpll_d2",
  345. "univpll1_d4",
  346. "syspll2_d2",
  347. "univpll_d7",
  348. "vencpll_d2"
  349. };
  350. static const char * const msdc30_3_parents[] = {
  351. "clk26m",
  352. "msdcpll2_ck",
  353. "msdcpll2_d2",
  354. "univpll2_d2",
  355. "msdcpll2_d4",
  356. "univpll1_d4",
  357. "syspll2_d2",
  358. "syspll_d7",
  359. "univpll_d7",
  360. "vencpll_d2",
  361. "msdcpll_ck",
  362. "msdcpll_d2",
  363. "msdcpll_d4"
  364. };
  365. static const char * const audio_parents[] = {
  366. "clk26m",
  367. "syspll3_d4",
  368. "syspll4_d4",
  369. "syspll1_d16"
  370. };
  371. static const char * const aud_intbus_parents[] = {
  372. "clk26m",
  373. "syspll1_d4",
  374. "syspll4_d2",
  375. "univpll3_d2",
  376. "univpll2_d8",
  377. "syspll3_d2",
  378. "syspll3_d4"
  379. };
  380. static const char * const pmicspi_parents[] = {
  381. "clk26m",
  382. "syspll1_d8",
  383. "syspll3_d4",
  384. "syspll1_d16",
  385. "univpll3_d4",
  386. "univpll_d26",
  387. "syspll3_d4"
  388. };
  389. static const char * const dpilvds1_parents[] = {
  390. "clk26m",
  391. "lvdspll2_ck",
  392. "lvdspll2_d2",
  393. "lvdspll2_d4",
  394. "lvdspll2_d8",
  395. "clkfpc"
  396. };
  397. static const char * const atb_parents[] = {
  398. "clk26m",
  399. "syspll1_d2",
  400. "univpll_d5",
  401. "syspll_d5"
  402. };
  403. static const char * const nr_parents[] = {
  404. "clk26m",
  405. "univpll1_d4",
  406. "syspll2_d2",
  407. "syspll1_d4",
  408. "univpll1_d8",
  409. "univpll3_d2",
  410. "univpll2_d2",
  411. "syspll_d5"
  412. };
  413. static const char * const nfi2x_parents[] = {
  414. "clk26m",
  415. "syspll4_d4",
  416. "univpll3_d4",
  417. "univpll1_d8",
  418. "syspll2_d4",
  419. "univpll3_d2",
  420. "syspll_d7",
  421. "syspll2_d2",
  422. "univpll2_d2",
  423. "syspll_d5",
  424. "syspll1_d2"
  425. };
  426. static const char * const irda_parents[] = {
  427. "clk26m",
  428. "univpll2_d4",
  429. "syspll2_d4",
  430. "univpll2_d8"
  431. };
  432. static const char * const cci400_parents[] = {
  433. "clk26m",
  434. "vencpll_ck",
  435. "armca35pll_600m",
  436. "armca35pll_400m",
  437. "univpll_d2",
  438. "syspll_d2",
  439. "msdcpll_ck",
  440. "univpll_d3"
  441. };
  442. static const char * const aud_1_parents[] = {
  443. "clk26m",
  444. "apll1_ck",
  445. "univpll2_d4",
  446. "univpll2_d8"
  447. };
  448. static const char * const aud_2_parents[] = {
  449. "clk26m",
  450. "apll2_ck",
  451. "univpll2_d4",
  452. "univpll2_d8"
  453. };
  454. static const char * const mem_mfg_parents[] = {
  455. "clk26m",
  456. "mmpll_ck",
  457. "univpll_d3"
  458. };
  459. static const char * const axi_mfg_parents[] = {
  460. "clk26m",
  461. "axi_sel",
  462. "univpll_d5"
  463. };
  464. static const char * const scam_parents[] = {
  465. "clk26m",
  466. "syspll3_d2",
  467. "univpll2_d4",
  468. "syspll2_d4"
  469. };
  470. static const char * const nfiecc_parents[] = {
  471. "clk26m",
  472. "nfi2x_sel",
  473. "syspll_d7",
  474. "syspll2_d2",
  475. "univpll2_d2",
  476. "univpll_d5",
  477. "syspll1_d2"
  478. };
  479. static const char * const pe2_mac_p0_parents[] = {
  480. "clk26m",
  481. "syspll1_d8",
  482. "syspll4_d2",
  483. "syspll2_d4",
  484. "univpll2_d4",
  485. "syspll3_d2"
  486. };
  487. static const char * const dpilvds_parents[] = {
  488. "clk26m",
  489. "lvdspll_ck",
  490. "lvdspll_d2",
  491. "lvdspll_d4",
  492. "lvdspll_d8",
  493. "clkfpc"
  494. };
  495. static const char * const hdcp_parents[] = {
  496. "clk26m",
  497. "syspll4_d2",
  498. "syspll3_d4",
  499. "univpll2_d4"
  500. };
  501. static const char * const hdcp_24m_parents[] = {
  502. "clk26m",
  503. "univpll_d26",
  504. "univpll_d52",
  505. "univpll2_d8"
  506. };
  507. static const char * const rtc_parents[] = {
  508. "clkrtc_int",
  509. "clkrtc_ext",
  510. "clk26m",
  511. "univpll3_d8"
  512. };
  513. static const char * const spinor_parents[] = {
  514. "clk26m",
  515. "clk26m_d2",
  516. "syspll4_d4",
  517. "univpll2_d8",
  518. "univpll3_d4",
  519. "syspll4_d2",
  520. "syspll2_d4",
  521. "univpll2_d4",
  522. "etherpll_125m",
  523. "syspll1_d4"
  524. };
  525. static const char * const apll_parents[] = {
  526. "clk26m",
  527. "apll1_ck",
  528. "apll1_d2",
  529. "apll1_d4",
  530. "apll1_d8",
  531. "apll1_d16",
  532. "apll2_ck",
  533. "apll2_d2",
  534. "apll2_d4",
  535. "apll2_d8",
  536. "apll2_d16",
  537. "clk26m",
  538. "clk26m"
  539. };
  540. static const char * const a1sys_hp_parents[] = {
  541. "clk26m",
  542. "apll1_ck",
  543. "apll1_d2",
  544. "apll1_d4",
  545. "apll1_d8",
  546. "apll1_d3"
  547. };
  548. static const char * const a2sys_hp_parents[] = {
  549. "clk26m",
  550. "apll2_ck",
  551. "apll2_d2",
  552. "apll2_d4",
  553. "apll2_d8",
  554. "apll2_d3"
  555. };
  556. static const char * const asm_l_parents[] = {
  557. "clk26m",
  558. "univpll2_d4",
  559. "univpll2_d2",
  560. "syspll_d5"
  561. };
  562. static const char * const i2so1_parents[] = {
  563. "clk26m",
  564. "apll1_ck",
  565. "apll2_ck"
  566. };
  567. static const char * const ether_125m_parents[] = {
  568. "clk26m",
  569. "etherpll_125m",
  570. "univpll3_d2"
  571. };
  572. static const char * const ether_50m_parents[] = {
  573. "clk26m",
  574. "etherpll_50m",
  575. "apll1_d3",
  576. "univpll3_d4"
  577. };
  578. static const char * const jpgdec_parents[] = {
  579. "clk26m",
  580. "univpll_d3",
  581. "tvdpll_429m",
  582. "vencpll_ck",
  583. "syspll_d3",
  584. "vcodecpll_ck",
  585. "univpll1_d2",
  586. "armca35pll_400m",
  587. "tvdpll_429m_d2",
  588. "tvdpll_429m_d4"
  589. };
  590. static const char * const spislv_parents[] = {
  591. "clk26m",
  592. "univpll2_d4",
  593. "univpll1_d4",
  594. "univpll2_d2",
  595. "univpll3_d2",
  596. "univpll1_d8",
  597. "univpll1_d2",
  598. "univpll_d5"
  599. };
  600. static const char * const ether_parents[] = {
  601. "clk26m",
  602. "etherpll_50m",
  603. "univpll_d26"
  604. };
  605. static const char * const di_parents[] = {
  606. "clk26m",
  607. "tvdpll_d2",
  608. "tvdpll_d4",
  609. "tvdpll_d8",
  610. "vencpll_ck",
  611. "vencpll_d2",
  612. "cvbs",
  613. "cvbs_d2"
  614. };
  615. static const char * const tvd_parents[] = {
  616. "clk26m",
  617. "cvbs_d2",
  618. "univpll2_d8"
  619. };
  620. static const char * const i2c_parents[] = {
  621. "clk26m",
  622. "univpll_d26",
  623. "univpll2_d4",
  624. "univpll3_d2",
  625. "univpll1_d4"
  626. };
  627. static const char * const msdc0p_aes_parents[] = {
  628. "clk26m",
  629. "syspll_d2",
  630. "univpll_d3",
  631. "vcodecpll_ck"
  632. };
  633. static const char * const cmsys_parents[] = {
  634. "clk26m",
  635. "univpll_d3",
  636. "syspll_d3",
  637. "syspll1_d2",
  638. "syspll2_d2"
  639. };
  640. static const char * const gcpu_parents[] = {
  641. "clk26m",
  642. "syspll_d3",
  643. "syspll1_d2",
  644. "univpll1_d2",
  645. "univpll_d5",
  646. "univpll3_d2",
  647. "univpll_d3"
  648. };
  649. static const char * const aud_apll1_parents[] = {
  650. "apll1",
  651. "clkaud_ext_i_1"
  652. };
  653. static const char * const aud_apll2_parents[] = {
  654. "apll2",
  655. "clkaud_ext_i_2"
  656. };
  657. static const char * const apll1_ref_parents[] = {
  658. "clkaud_ext_i_2",
  659. "clkaud_ext_i_1",
  660. "clki2si0_mck_i",
  661. "clki2si1_mck_i",
  662. "clki2si2_mck_i",
  663. "clktdmin_mclk_i",
  664. "clki2si2_mck_i",
  665. "clktdmin_mclk_i"
  666. };
  667. static const char * const audull_vtx_parents[] = {
  668. "d2a_ulclk_6p5m",
  669. "clkaud_ext_i_0"
  670. };
  671. static struct mtk_composite top_muxes[] = {
  672. /* CLK_CFG_0 */
  673. MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
  674. 7, CLK_IS_CRITICAL),
  675. MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
  676. 15, CLK_IS_CRITICAL),
  677. MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
  678. mm_parents, 0x040, 24, 3, 31),
  679. /* CLK_CFG_1 */
  680. MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
  681. pwm_parents, 0x050, 0, 2, 7),
  682. MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
  683. vdec_parents, 0x050, 8, 4, 15),
  684. MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
  685. venc_parents, 0x050, 16, 4, 23),
  686. MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
  687. mfg_parents, 0x050, 24, 4, 31),
  688. /* CLK_CFG_2 */
  689. MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
  690. camtg_parents, 0x060, 0, 4, 7),
  691. MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
  692. uart_parents, 0x060, 8, 1, 15),
  693. MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
  694. spi_parents, 0x060, 16, 3, 23),
  695. MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
  696. usb20_parents, 0x060, 24, 2, 31),
  697. /* CLK_CFG_3 */
  698. MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
  699. usb30_parents, 0x070, 0, 2, 7),
  700. MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
  701. msdc50_0_h_parents, 0x070, 8, 3, 15),
  702. MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
  703. msdc50_0_parents, 0x070, 16, 4, 23),
  704. MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
  705. msdc30_1_parents, 0x070, 24, 3, 31),
  706. /* CLK_CFG_4 */
  707. MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
  708. msdc30_1_parents, 0x080, 0, 3, 7),
  709. MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
  710. msdc30_3_parents, 0x080, 8, 4, 15),
  711. MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
  712. audio_parents, 0x080, 16, 2, 23),
  713. MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
  714. aud_intbus_parents, 0x080, 24, 3, 31),
  715. /* CLK_CFG_5 */
  716. MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
  717. pmicspi_parents, 0x090, 0, 3, 7),
  718. MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
  719. dpilvds1_parents, 0x090, 8, 3, 15),
  720. MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
  721. atb_parents, 0x090, 16, 2, 23),
  722. MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
  723. nr_parents, 0x090, 24, 3, 31),
  724. /* CLK_CFG_6 */
  725. MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
  726. nfi2x_parents, 0x0a0, 0, 4, 7),
  727. MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
  728. irda_parents, 0x0a0, 8, 2, 15),
  729. MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
  730. cci400_parents, 0x0a0, 16, 3, 23),
  731. MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
  732. aud_1_parents, 0x0a0, 24, 2, 31),
  733. /* CLK_CFG_7 */
  734. MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
  735. aud_2_parents, 0x0b0, 0, 2, 7),
  736. MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
  737. mem_mfg_parents, 0x0b0, 8, 2, 15),
  738. MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
  739. axi_mfg_parents, 0x0b0, 16, 2, 23),
  740. MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
  741. scam_parents, 0x0b0, 24, 2, 31),
  742. /* CLK_CFG_8 */
  743. MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
  744. nfiecc_parents, 0x0c0, 0, 3, 7),
  745. MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
  746. pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
  747. MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
  748. pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
  749. MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
  750. dpilvds_parents, 0x0c0, 24, 3, 31),
  751. /* CLK_CFG_9 */
  752. MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
  753. msdc50_0_h_parents, 0x0d0, 0, 3, 7),
  754. MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
  755. hdcp_parents, 0x0d0, 8, 2, 15),
  756. MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
  757. hdcp_24m_parents, 0x0d0, 16, 2, 23),
  758. MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
  759. 31, CLK_IS_CRITICAL),
  760. /* CLK_CFG_10 */
  761. MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
  762. spinor_parents, 0x500, 0, 4, 7),
  763. MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
  764. apll_parents, 0x500, 8, 4, 15),
  765. MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
  766. apll_parents, 0x500, 16, 4, 23),
  767. MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
  768. a1sys_hp_parents, 0x500, 24, 3, 31),
  769. /* CLK_CFG_11 */
  770. MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
  771. a2sys_hp_parents, 0x510, 0, 3, 7),
  772. MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
  773. asm_l_parents, 0x510, 8, 2, 15),
  774. MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
  775. asm_l_parents, 0x510, 16, 2, 23),
  776. MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
  777. asm_l_parents, 0x510, 24, 2, 31),
  778. /* CLK_CFG_12 */
  779. MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
  780. i2so1_parents, 0x520, 0, 2, 7),
  781. MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
  782. i2so1_parents, 0x520, 8, 2, 15),
  783. MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
  784. i2so1_parents, 0x520, 16, 2, 23),
  785. MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
  786. i2so1_parents, 0x520, 24, 2, 31),
  787. /* CLK_CFG_13 */
  788. MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
  789. i2so1_parents, 0x530, 0, 2, 7),
  790. MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
  791. i2so1_parents, 0x530, 8, 2, 15),
  792. MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
  793. i2so1_parents, 0x530, 16, 2, 23),
  794. MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
  795. i2so1_parents, 0x530, 24, 2, 31),
  796. /* CLK_CFG_14 */
  797. MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
  798. ether_125m_parents, 0x540, 0, 2, 7),
  799. MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
  800. ether_50m_parents, 0x540, 8, 2, 15),
  801. MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
  802. jpgdec_parents, 0x540, 16, 4, 23),
  803. MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
  804. spislv_parents, 0x540, 24, 3, 31),
  805. /* CLK_CFG_15 */
  806. MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
  807. ether_parents, 0x550, 0, 2, 7),
  808. MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
  809. camtg_parents, 0x550, 8, 4, 15),
  810. MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
  811. di_parents, 0x550, 16, 3, 23),
  812. MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
  813. tvd_parents, 0x550, 24, 2, 31),
  814. /* CLK_CFG_16 */
  815. MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
  816. i2c_parents, 0x560, 0, 3, 7),
  817. MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
  818. pwm_parents, 0x560, 8, 2, 15),
  819. MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
  820. msdc0p_aes_parents, 0x560, 16, 2, 23),
  821. MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
  822. cmsys_parents, 0x560, 24, 3, 31),
  823. /* CLK_CFG_17 */
  824. MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
  825. gcpu_parents, 0x570, 0, 3, 7),
  826. /* CLK_AUDDIV_4 */
  827. MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
  828. aud_apll1_parents, 0x134, 0, 1),
  829. MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
  830. aud_apll2_parents, 0x134, 1, 1),
  831. MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
  832. audull_vtx_parents, 0x134, 31, 1),
  833. MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
  834. apll1_ref_parents, 0x134, 4, 3),
  835. MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
  836. apll1_ref_parents, 0x134, 7, 3),
  837. };
  838. static const char * const mcu_mp0_parents[] = {
  839. "clk26m",
  840. "armca35pll_ck",
  841. "f_mp0_pll1_ck",
  842. "f_mp0_pll2_ck"
  843. };
  844. static const char * const mcu_mp2_parents[] = {
  845. "clk26m",
  846. "armca72pll_ck",
  847. "f_big_pll1_ck",
  848. "f_big_pll2_ck"
  849. };
  850. static const char * const mcu_bus_parents[] = {
  851. "clk26m",
  852. "cci400_sel",
  853. "f_bus_pll1_ck",
  854. "f_bus_pll2_ck"
  855. };
  856. static struct mtk_composite mcu_muxes[] = {
  857. /* mp0_pll_divider_cfg */
  858. MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
  859. 9, 2, -1, CLK_IS_CRITICAL),
  860. /* mp2_pll_divider_cfg */
  861. MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
  862. 9, 2, -1, CLK_IS_CRITICAL),
  863. /* bus_pll_divider_cfg */
  864. MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
  865. 9, 2, -1, CLK_IS_CRITICAL),
  866. };
  867. static const struct mtk_clk_divider top_adj_divs[] = {
  868. DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
  869. DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
  870. DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
  871. DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
  872. DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
  873. DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
  874. DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
  875. DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
  876. };
  877. static const struct mtk_gate_regs top0_cg_regs = {
  878. .set_ofs = 0x120,
  879. .clr_ofs = 0x120,
  880. .sta_ofs = 0x120,
  881. };
  882. static const struct mtk_gate_regs top1_cg_regs = {
  883. .set_ofs = 0x424,
  884. .clr_ofs = 0x424,
  885. .sta_ofs = 0x424,
  886. };
  887. #define GATE_TOP0(_id, _name, _parent, _shift) { \
  888. .id = _id, \
  889. .name = _name, \
  890. .parent_name = _parent, \
  891. .regs = &top0_cg_regs, \
  892. .shift = _shift, \
  893. .ops = &mtk_clk_gate_ops_no_setclr, \
  894. }
  895. #define GATE_TOP1(_id, _name, _parent, _shift) { \
  896. .id = _id, \
  897. .name = _name, \
  898. .parent_name = _parent, \
  899. .regs = &top1_cg_regs, \
  900. .shift = _shift, \
  901. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  902. }
  903. static const struct mtk_gate top_clks[] = {
  904. /* TOP0 */
  905. GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
  906. GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
  907. GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
  908. GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
  909. GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
  910. GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
  911. GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
  912. GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
  913. /* TOP1 */
  914. GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
  915. GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
  916. GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
  917. };
  918. static const struct mtk_gate_regs infra_cg_regs = {
  919. .set_ofs = 0x40,
  920. .clr_ofs = 0x44,
  921. .sta_ofs = 0x48,
  922. };
  923. #define GATE_INFRA(_id, _name, _parent, _shift) { \
  924. .id = _id, \
  925. .name = _name, \
  926. .parent_name = _parent, \
  927. .regs = &infra_cg_regs, \
  928. .shift = _shift, \
  929. .ops = &mtk_clk_gate_ops_setclr, \
  930. }
  931. static const struct mtk_gate infra_clks[] = {
  932. GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
  933. GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
  934. GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
  935. GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
  936. GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
  937. GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
  938. GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
  939. };
  940. static const struct mtk_gate_regs peri0_cg_regs = {
  941. .set_ofs = 0x8,
  942. .clr_ofs = 0x10,
  943. .sta_ofs = 0x18,
  944. };
  945. static const struct mtk_gate_regs peri1_cg_regs = {
  946. .set_ofs = 0xc,
  947. .clr_ofs = 0x14,
  948. .sta_ofs = 0x1c,
  949. };
  950. static const struct mtk_gate_regs peri2_cg_regs = {
  951. .set_ofs = 0x42c,
  952. .clr_ofs = 0x42c,
  953. .sta_ofs = 0x42c,
  954. };
  955. #define GATE_PERI0(_id, _name, _parent, _shift) { \
  956. .id = _id, \
  957. .name = _name, \
  958. .parent_name = _parent, \
  959. .regs = &peri0_cg_regs, \
  960. .shift = _shift, \
  961. .ops = &mtk_clk_gate_ops_setclr, \
  962. }
  963. #define GATE_PERI1(_id, _name, _parent, _shift) { \
  964. .id = _id, \
  965. .name = _name, \
  966. .parent_name = _parent, \
  967. .regs = &peri1_cg_regs, \
  968. .shift = _shift, \
  969. .ops = &mtk_clk_gate_ops_setclr, \
  970. }
  971. #define GATE_PERI2(_id, _name, _parent, _shift) { \
  972. .id = _id, \
  973. .name = _name, \
  974. .parent_name = _parent, \
  975. .regs = &peri2_cg_regs, \
  976. .shift = _shift, \
  977. .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  978. }
  979. static const struct mtk_gate peri_clks[] = {
  980. /* PERI0 */
  981. GATE_PERI0(CLK_PERI_NFI, "per_nfi",
  982. "axi_sel", 0),
  983. GATE_PERI0(CLK_PERI_THERM, "per_therm",
  984. "axi_sel", 1),
  985. GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
  986. "pwm_sel", 2),
  987. GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
  988. "pwm_sel", 3),
  989. GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
  990. "pwm_sel", 4),
  991. GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
  992. "pwm_sel", 5),
  993. GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
  994. "pwm_sel", 6),
  995. GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
  996. "pwm_sel", 7),
  997. GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
  998. "pwm_sel", 8),
  999. GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
  1000. "pwm_sel", 9),
  1001. GATE_PERI0(CLK_PERI_PWM, "per_pwm",
  1002. "pwm_sel", 10),
  1003. GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
  1004. "axi_sel", 13),
  1005. GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
  1006. "msdc50_0_sel", 14),
  1007. GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
  1008. "msdc30_1_sel", 15),
  1009. GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
  1010. "msdc30_2_sel", 16),
  1011. GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
  1012. "msdc30_3_sel", 17),
  1013. GATE_PERI0(CLK_PERI_UART0, "per_uart0",
  1014. "uart_sel", 20),
  1015. GATE_PERI0(CLK_PERI_UART1, "per_uart1",
  1016. "uart_sel", 21),
  1017. GATE_PERI0(CLK_PERI_UART2, "per_uart2",
  1018. "uart_sel", 22),
  1019. GATE_PERI0(CLK_PERI_UART3, "per_uart3",
  1020. "uart_sel", 23),
  1021. GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
  1022. "axi_sel", 24),
  1023. GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
  1024. "axi_sel", 25),
  1025. GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
  1026. "axi_sel", 26),
  1027. GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
  1028. "axi_sel", 27),
  1029. GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
  1030. "axi_sel", 28),
  1031. GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
  1032. "ltepll_fs26m", 29),
  1033. GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
  1034. "spi_sel", 30),
  1035. /* PERI1 */
  1036. GATE_PERI1(CLK_PERI_SPI, "per_spi",
  1037. "spinor_sel", 1),
  1038. GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
  1039. "axi_sel", 3),
  1040. GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
  1041. "spi_sel", 5),
  1042. GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
  1043. "spi_sel", 6),
  1044. GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
  1045. "spi_sel", 8),
  1046. GATE_PERI1(CLK_PERI_UART4, "per_uart4",
  1047. "uart_sel", 9),
  1048. GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
  1049. "uart_sel", 11),
  1050. GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
  1051. "uart_sel", 12),
  1052. GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
  1053. "uart_sel", 14),
  1054. GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
  1055. "uart_sel", 15),
  1056. GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
  1057. "uart_sel", 16),
  1058. /* PERI2 */
  1059. GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
  1060. "msdc50_0_sel", 0),
  1061. GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
  1062. "msdc30_1_sel", 1),
  1063. GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
  1064. "msdc30_2_sel", 2),
  1065. GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
  1066. "msdc30_3_sel", 3),
  1067. GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
  1068. "msdc50_0_h_sel", 4),
  1069. GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
  1070. "msdc50_3_h_sel", 5),
  1071. GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
  1072. "axi_sel", 6),
  1073. GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
  1074. "mem_sel", 7),
  1075. };
  1076. #define MT2712_PLL_FMAX (3000UL * MHZ)
  1077. #define CON0_MT2712_RST_BAR BIT(24)
  1078. #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  1079. _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
  1080. _tuner_en_bit, _pcw_reg, _pcw_shift, \
  1081. _div_table) { \
  1082. .id = _id, \
  1083. .name = _name, \
  1084. .reg = _reg, \
  1085. .pwr_reg = _pwr_reg, \
  1086. .en_mask = _en_mask, \
  1087. .flags = _flags, \
  1088. .rst_bar_mask = CON0_MT2712_RST_BAR, \
  1089. .fmax = MT2712_PLL_FMAX, \
  1090. .pcwbits = _pcwbits, \
  1091. .pd_reg = _pd_reg, \
  1092. .pd_shift = _pd_shift, \
  1093. .tuner_reg = _tuner_reg, \
  1094. .tuner_en_reg = _tuner_en_reg, \
  1095. .tuner_en_bit = _tuner_en_bit, \
  1096. .pcw_reg = _pcw_reg, \
  1097. .pcw_shift = _pcw_shift, \
  1098. .div_table = _div_table, \
  1099. }
  1100. #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
  1101. _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
  1102. _tuner_en_bit, _pcw_reg, _pcw_shift) \
  1103. PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
  1104. _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
  1105. _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
  1106. _pcw_shift, NULL)
  1107. static const struct mtk_pll_div_table armca35pll_div_table[] = {
  1108. { .div = 0, .freq = MT2712_PLL_FMAX },
  1109. { .div = 1, .freq = 1202500000 },
  1110. { .div = 2, .freq = 500500000 },
  1111. { .div = 3, .freq = 315250000 },
  1112. { .div = 4, .freq = 157625000 },
  1113. { } /* sentinel */
  1114. };
  1115. static const struct mtk_pll_div_table armca72pll_div_table[] = {
  1116. { .div = 0, .freq = MT2712_PLL_FMAX },
  1117. { .div = 1, .freq = 994500000 },
  1118. { .div = 2, .freq = 520000000 },
  1119. { .div = 3, .freq = 315250000 },
  1120. { .div = 4, .freq = 157625000 },
  1121. { } /* sentinel */
  1122. };
  1123. static const struct mtk_pll_div_table mmpll_div_table[] = {
  1124. { .div = 0, .freq = MT2712_PLL_FMAX },
  1125. { .div = 1, .freq = 1001000000 },
  1126. { .div = 2, .freq = 601250000 },
  1127. { .div = 3, .freq = 250250000 },
  1128. { .div = 4, .freq = 125125000 },
  1129. { } /* sentinel */
  1130. };
  1131. static const struct mtk_pll_data plls[] = {
  1132. PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
  1133. HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
  1134. PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
  1135. HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
  1136. PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
  1137. 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
  1138. PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
  1139. 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
  1140. PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
  1141. 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
  1142. PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
  1143. 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
  1144. PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
  1145. 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
  1146. PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
  1147. 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
  1148. PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
  1149. 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
  1150. PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
  1151. 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
  1152. PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
  1153. 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
  1154. PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
  1155. 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
  1156. mmpll_div_table),
  1157. PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
  1158. HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
  1159. armca35pll_div_table),
  1160. PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
  1161. 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
  1162. armca72pll_div_table),
  1163. PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
  1164. 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
  1165. };
  1166. static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
  1167. {
  1168. struct clk_onecell_data *clk_data;
  1169. int r;
  1170. struct device_node *node = pdev->dev.of_node;
  1171. clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
  1172. mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
  1173. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1174. if (r != 0)
  1175. pr_err("%s(): could not register clock provider: %d\n",
  1176. __func__, r);
  1177. return r;
  1178. }
  1179. static struct clk_onecell_data *top_clk_data;
  1180. static void clk_mt2712_top_init_early(struct device_node *node)
  1181. {
  1182. int r, i;
  1183. if (!top_clk_data) {
  1184. top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
  1185. for (i = 0; i < CLK_TOP_NR_CLK; i++)
  1186. top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
  1187. }
  1188. mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
  1189. top_clk_data);
  1190. r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
  1191. if (r)
  1192. pr_err("%s(): could not register clock provider: %d\n",
  1193. __func__, r);
  1194. }
  1195. CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
  1196. clk_mt2712_top_init_early);
  1197. static int clk_mt2712_top_probe(struct platform_device *pdev)
  1198. {
  1199. int r, i;
  1200. struct device_node *node = pdev->dev.of_node;
  1201. void __iomem *base;
  1202. base = devm_platform_ioremap_resource(pdev, 0);
  1203. if (IS_ERR(base)) {
  1204. pr_err("%s(): ioremap failed\n", __func__);
  1205. return PTR_ERR(base);
  1206. }
  1207. if (!top_clk_data) {
  1208. top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
  1209. } else {
  1210. for (i = 0; i < CLK_TOP_NR_CLK; i++) {
  1211. if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
  1212. top_clk_data->clks[i] = ERR_PTR(-ENOENT);
  1213. }
  1214. }
  1215. mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  1216. top_clk_data);
  1217. mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
  1218. top_clk_data);
  1219. mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
  1220. mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
  1221. &mt2712_clk_lock, top_clk_data);
  1222. mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
  1223. &mt2712_clk_lock, top_clk_data);
  1224. mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
  1225. top_clk_data);
  1226. r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
  1227. if (r != 0)
  1228. pr_err("%s(): could not register clock provider: %d\n",
  1229. __func__, r);
  1230. return r;
  1231. }
  1232. static int clk_mt2712_infra_probe(struct platform_device *pdev)
  1233. {
  1234. struct clk_onecell_data *clk_data;
  1235. int r;
  1236. struct device_node *node = pdev->dev.of_node;
  1237. clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
  1238. mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
  1239. clk_data);
  1240. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1241. if (r != 0)
  1242. pr_err("%s(): could not register clock provider: %d\n",
  1243. __func__, r);
  1244. mtk_register_reset_controller(node, 2, 0x30);
  1245. return r;
  1246. }
  1247. static int clk_mt2712_peri_probe(struct platform_device *pdev)
  1248. {
  1249. struct clk_onecell_data *clk_data;
  1250. int r;
  1251. struct device_node *node = pdev->dev.of_node;
  1252. clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
  1253. mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
  1254. clk_data);
  1255. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1256. if (r != 0)
  1257. pr_err("%s(): could not register clock provider: %d\n",
  1258. __func__, r);
  1259. mtk_register_reset_controller(node, 2, 0);
  1260. return r;
  1261. }
  1262. static int clk_mt2712_mcu_probe(struct platform_device *pdev)
  1263. {
  1264. struct clk_onecell_data *clk_data;
  1265. int r;
  1266. struct device_node *node = pdev->dev.of_node;
  1267. void __iomem *base;
  1268. base = devm_platform_ioremap_resource(pdev, 0);
  1269. if (IS_ERR(base)) {
  1270. pr_err("%s(): ioremap failed\n", __func__);
  1271. return PTR_ERR(base);
  1272. }
  1273. clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
  1274. mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
  1275. &mt2712_clk_lock, clk_data);
  1276. r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  1277. if (r != 0)
  1278. pr_err("%s(): could not register clock provider: %d\n",
  1279. __func__, r);
  1280. return r;
  1281. }
  1282. static const struct of_device_id of_match_clk_mt2712[] = {
  1283. {
  1284. .compatible = "mediatek,mt2712-apmixedsys",
  1285. .data = clk_mt2712_apmixed_probe,
  1286. }, {
  1287. .compatible = "mediatek,mt2712-topckgen",
  1288. .data = clk_mt2712_top_probe,
  1289. }, {
  1290. .compatible = "mediatek,mt2712-infracfg",
  1291. .data = clk_mt2712_infra_probe,
  1292. }, {
  1293. .compatible = "mediatek,mt2712-pericfg",
  1294. .data = clk_mt2712_peri_probe,
  1295. }, {
  1296. .compatible = "mediatek,mt2712-mcucfg",
  1297. .data = clk_mt2712_mcu_probe,
  1298. }, {
  1299. /* sentinel */
  1300. }
  1301. };
  1302. static int clk_mt2712_probe(struct platform_device *pdev)
  1303. {
  1304. int (*clk_probe)(struct platform_device *);
  1305. int r;
  1306. clk_probe = of_device_get_match_data(&pdev->dev);
  1307. if (!clk_probe)
  1308. return -EINVAL;
  1309. r = clk_probe(pdev);
  1310. if (r != 0)
  1311. dev_err(&pdev->dev,
  1312. "could not register clock provider: %s: %d\n",
  1313. pdev->name, r);
  1314. return r;
  1315. }
  1316. static struct platform_driver clk_mt2712_drv = {
  1317. .probe = clk_mt2712_probe,
  1318. .driver = {
  1319. .name = "clk-mt2712",
  1320. .of_match_table = of_match_clk_mt2712,
  1321. },
  1322. };
  1323. static int __init clk_mt2712_init(void)
  1324. {
  1325. return platform_driver_register(&clk_mt2712_drv);
  1326. }
  1327. arch_initcall(clk_mt2712_init);